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Education
Ph.D. 1977, Electrical Engineering, University of Illinois, Urbana-Champaign
M.S. 1972, Electrical Engineering, Stanford University
B.S. 1971, Electrical Engineering, Montana State University
Research Interests
Biologically inspired information engineering at the molecular scale; Intelligent Signal Processing; Hybrid Nanoscale/CMOS VLSI for Intelligent Signal Processing (ISP); Sensor electronics and data processing, Parallel processing of image processing and pattern recognition.
Selected Publications
C. Gao and D. Hammerstrom, "Cortical Models onto CMOL and CMOS – Architectures and Performance/price," Submitted to IEEE Transactions on Circuits and Systems – I: Regular Papers, a Special Issue Nanoelectronic Circuits and Nanoarchitectures, Nov. 2007.
I. Bahar, J. Harlow, D. Hammerstrom, W. Joyner, C. Lau, D. Marculescu, A. Orailoglu, and M. Pedram, "Architectures for Silicon Nanoelectronics and Beyond," to be published in
IEEE Computer, January 2007
.
H. Luk, D. Hammerstrom, C. Gao, M. Pavel, D. Kerr, "Biologically Inspired Enhanced Vision System (EVS) for Aircraft Landing Guidance," International Joint Conference on Neural Networks, vol. 2004, 2004.
J. Carruthers, D. Hammerstrom, B. Colwell, G. Bourianoff, V. Zhirnov, "Technology Scaling and Computer Architecture Implementations in Semiconductors," International Technology Roadmap for Semiconductors, Architecture Working Group White Paper, 2003.
S. Zhu, D. Hammerstrom, "Reinforcement Learning in Associative Memory," International Joint Conference on Neural Networks, vol. 2003, 2003.
C. Gao, D. Hammerstrom, "Platform Performance Comparison of PALM Network on Pentium 4 and FP," International Joint Conference on Neural Networks, vol. 2003, 2003.
J. Richard Kerr, C. Hung Luk, D. Hammerstrom, M. Pavel, "Advanced integrated enhanced vision systems," SPIE Aerosense, vol. Specific Conference (no. 5081): Enhanced and Synthetic Vision, 2003.
C. Gao, D. Hammerstrom, S. Zhu, M. Butts, "FPGA Implementation Of Very Large Associative Memories - Scaling Issues," Book Chapter in FPGA Implementations of Neural Networks, 2003.
