Faculty Research Interests and
Selected Publications

 

Malgorzata Chrzanowska-Jeske Professor
Senior IEEE Member

Phone: 503.725.5415
Fax: 503.725.3807
Email: jeske@ece.pdx.edu
Office: FAB 160-04
Web site: http://www.ee.pdx.edu/~jeske/

Education
Ph.D. 1988, Electrical Engineering, Auburn University
M.S. 1976, Electrical Engineering, Tuskegee Institute
M.S. 1972, Electronic Engineering, Technical University of Warsaw

Research Interests
VLSI physical design automation, Design for Manufacturability and Design for Yield, layout driven-logic synthesis, regular layout design methodologies, Design for Testability, and design and DA for low power, nano CMOS and nanotechnologies in the presence of variations. Design methodologies and tools for System-on-Chip, System-in-Package, System-on-Package, 3D ICs, and Lab-on-Chip designs for biomedical applications.

Selected Publications
R. Nain, M. Chrzanowska-Jeske, "Fast Placement-aware 3D Floorplanning using Vertical Constraints on Sequence Pairs," IEEE Trans. On Very Large Scale Integration Systems,  vol.PP, no.99, pp.1-14, 0, 2010.

R. Ashraf, M. Chrzanowska-Jeske, S. G. Narendra, "Functional yield Estimation of carbon nanotube-based logic Gates in the Presence of Defects" IEEE Trans. On Nanotechnology, vol.9, no.6, pp.687-700, Nov. 2010.

T. Wan and M. Chrzanowska-Jeske, "A Novel Net-Degree Distribution Model and its Application to Floorplanning Benchmark Generation," Integration, the VLSI Journal, Vol. 40, pp. 420-433, July 2007.

J. S. Zhang, A. Mishchenko, Robert Brayton and M. Chrzanowska-Jeske "Symmetry Detection for Large Boolean Functions Using Circuit Representation, Simulation and Satisfiability," Proc. of the IEEE Design Automation Conference, DAC06, July 2006.

J. S. Zhang, M. Chrzanowska-Jeske, A. Mishchenko J, Burch, "Linear Cofactor Relationships in Boolean Functions," The IEEE Trans. On CAD on Integrated Circuits and Systems, vol. 25, no 6, pp. 1011- 1023, June 2006.

A. Mishchenko, J. S. Zhang, S. Sinha, J. R. Burch, R. Brayton, and M. Chrzanowska-Jeske, "Using Simulation and Satisfability to Compute Flexibilities in Boolean Networks," The IEEE Trans. On CAD on Integrated Circuits and Systems, vol. 25, no. 5, pp. 743-755, May, 2006.

G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske, J. S. Zhang, "Substrate Noise Modeling in Early Floorplanning of MS-SOCs," Proceedings of the IEEE ASP-DAC, January 2005.

Y. Xia, M. Chrzanowska-Jeske,  B. Wang M. Jeske, "Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints," Proceedings of IEEE International Conference on CAD, ICCAD 2003.

F. Rafiq, M. Chrzanowska-Jeske,  H. H. Yang, M. Jeske, N. Sherwani, "Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Designs,"  IEEE Trans on Computer-Aided-Design, Vol. 22, nr. 6, pp 730-741, 2003.