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References

1
Abadir, M.S., Breuer. M.A.: "A Knowledge-Based System for Designing Testable VLSI Chips", IEEE Design & Test, pp.56-68, August 1985.

2
Agrawal, P., Meyer, M.J.: "Automation in the Design of Finite-State Machines", VLSI Design, Vol.5, pp. 74-84, Sept. 1984.

3
Albicki, A.: "Computer Method for Minimization of Number of States of an Automaton", Ph.D. Thesis, Faculty of Electronics, Warsaw Technical University, Warsaw, 1973 (in Polish).

4
Almaini, A.E.A., Moosa, M.A., Aziz, N.M.: "Computer Aided Design of Groups of Exclusive Logic Functions", Digital Processes, Vol.6, pp. 227-243, 1980.

5
Ashenhurst, R.L.: "The Decomposition of Switching Functions", Proceedings. Int. Symp. on the Theory of Switching, pp.74-116, April 1957.

6
Armstrong, D.B.: "A Programmed Algorithm for Assigning Internal Codes to Sequential Machines", IRE Transactions Electr. Comp., Vol. EC-11, pp. 466-472, August 1962.

7
Armstrong, D.B.: "On the Efficient Assignment of Internal Codes to Sequential Machines", IRE Transactions on Electronic Computers, Vol. EC-11, pp. 611-622, October 1962.

8
Barthel, D.: "A Remark Concerning Minimization of Expressions of Boolean Algebra in the Case of DON'T-CARE Conditions", Elektron. Informationsverarb. Kybern. , Germany, Vol. 19., No.7-8, pp.393-396.

9
Baugh, C.R.: "Generation of Representative Functions of the NPN Equivalence Classes of Unate Boolean Functions", IEEE Trans. on Comp., Vol. C-21, No.12., pp. 1373-1379, December 1972.

10
Bendas, J.B.: "Design Through Transformation", Proc. 20th Design Automation Conference, June 1983, pp. 253-256.

11
Bennets, R.G.: "An Improved Method of Prime C-Class Derivation in the State Reduction of Sequential Networks", IEEE Trans. Computers, Vol. C-20, pp.229-231, 1971.

12
Bennets, R.G., Washington, J.L.,Lewin, D.W.: "A Computer Algorithm for State-Table Reduction", Radio Electron. Engn. Vol.42, pp.513-520, 1972.

13
Besslich, P.W.: "Efficient Computer Method for EXOR Logic Design", IEE Proc. , Vol. 130, Pt.E, No.6, November 1983.

14
Biswas, N.N.: "Implication Trees in the Minimization of Incompletely Specified Sequential Machines", Int. J. Electron. (GB), No.2, pp.291-298, August 1983.

15
Blank, J., Fox, J., Blackman, T., Ciesielski, M., Markov, L.: "The Silc Silicon Compiler", GTE Laboratories Profile , September 1984.

16
Bouchet, A.: "An Algebraic Method for Minimizing the Number of States in an Incomplete Sequential Machine", IEEE Trans. Computers, Vol. C-17, pp. 795-798, 1968.

17
Brand, D.: "Redundancy and Don't Cares in Logic Synthesis", IEEE Trans. Computers, Vol.C-32, No.10, pp.947-952, October 1983.

18
Breitbart, Y., Vairavan, R.: "The Computational Complexity of a Class of Minimization Algorithms for Switching Functions", IEEE Trans. on Comp., Vol. C-20, No. 12, pp. 941-943, December 1979.

19
Brand, D., Griffin W.: "Synthesis of Circuit Families with Open Book Set", Proceeding Second Int. Symp. on VLSI Tech. Syst. and Appl. Taipei, Taiwan, May 1985.

20
Brayton, R.K., McMullen, C.T.: "The Decomposition and Factorization of Boolean Expressions", Proc. of 1982 ISCAS Symp., Rome, pp.49-54, May 1982.

21
Brayton, R.K., Hachtel, G.D., Hemachandra, L.A., Newton, A.R., Sangiovanni-Vincentelli, A.L.M.: "A Comparison of Logic Minimization Strategies Using ESPRESSO: An APL Program Package for Partitioned Logic Minimization", Proc. of 1982 ISCAS Symp., Rome, pp.42-48, May 1982.

22
Brayton, R.K., Cohen, J.D., Hachtel, G.D., Trager, B.M., Yun, D.Y.Y.: "Fast Recursive Boolean Function Manipulation", Proc. of 1982 ISCAS Symp., Rome, pp.58-62, May 1982.

23
Brayton, R.K., et al: "Automated Implementation of Switching Functions as Dynamic CMOS Circuits", Proc. 1984 IEEE Cust. Int. Circ. Conf. Rochester, NY., May 1984.

24
Brayton, R.K., Hachtel, G.D., McMullen, C.T., Sangiovanni-Vincentelli, A.L.: "Logic Minimization Algorithms for VLSI Synthesis", Kluwer Academic Publishers, 1984.

25
Brayton, R.K., McMullen, C.T.: "Synthesis and Optimization of Multistage Logic", Proc. 1984 Int. Conf. on Comp. Des., pp.23-30, Rye, NY ,October 1984.

26
Breuer, M.A. (ed.).: "Design Automation of Digital Systems". Vol. 1, Prentice Hall, Englewood Cliffs, New Jersey, 1972.

27
Brown, D.: "A State Machine Synthesizer", Proc. 18th Des. Aut. Conf. Nashville, June 1981.

28
Bruck, R., Kleinjohann, B., Kathofer, T., Rammig, F.J.: "Synthesis of Concurrent Modular Controllers from Algorithmic Descriptions, Proc. 23rd Design Automation Conf., pp. 285-292, June 29-July 2, Las Vegas 1986.

29
Bryant, R.E.: "Symbolic Manipulation of Boolean Functions Using a Graphical Representation", Proc. 22nd Design Automation Conference, IEEE 1985, pp. 688-694.

30
Brzozowski,: "Derivatives of Regular Expressions", J. Assoc. Computing Machinery, Vol. 11, pp. 481-494, 1964.

31
Cerny, E., Marin, M.A.: "A Computer Algorithm for the Synthesis of Memoryless Logic Circuits", IEEE Trans. on Comp. , Vol. ??, pp. 455-465, May 1974.

32
Cioffi, g., Constantini, E., DeJiulio, S.: "A New Approach to the Decomposition of Sequential Systems", Digital Processes, Vol. 3, pp. 35-48, 1977.

33
Clocksin, W.F., Mellish, C.S.: "Programming in Prolog". Springer-Verlag, Berlin, Heidelberg, New York. 1981.

34
Cohen, W., Barlett, K., deGeus, A.J.: "Impact of Metarules in a Rule Based Expert System for Gate Level Optimization", Proc. Intern. Symp. on Circuits and Systems, May 1985.

35
Cohoon, J., Sahni, S.: "Heuristics For The Circuit Realization Problem", Proc. 20th Design Automation Conference, IEEE 1983, pp. 560-566.

36
Coppola, A.J.: "An Implementation of a State Assignment Heuristic", Proc. of the 23-rd Design Automation Conference, pp. 643-649, June 29 - July 2, 1986.

37
Crist, S.C.: "Synthesis of Combinational Logic Using Decomposition and Probability", IEEE Trans. on Comp., Vol. C-29, No. 11, pp. 1013-1016, November 1980.

38
Curtis, H.A.: "Design of Switching Circuits", Van Nostrand, Princeton N.J., 1962.

39
Curtis, H.A.: "Generalized Tree Circuit - The Basic Building Block of an Extended Decomposition Theory", JACM, 1963.

40
Curtis, H.A.: "Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part 1", IEEE Trans. on Comp. Vol. C-18, pp. 1121-1127, December 1969.

41
Curtis, H.A.: "Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part 2", IEEE Trans. on Comp. Vol. C-19, pp. 66-73, January 1970.

42
Dagenais, M.R., Agarwal, V.K., Rumin N.C.: "The McBoole Logic Minimizer", Proc. 22nd Design Automation Conference, IEEE 1985, pp. 667-673.

43
Daisy Corp.: "Personal Logician", 700 Middlefield Road, P.O. Box 7006, Mountain View, CA 94039-7006.

44
Darringer, J., Joyner, W.H., Jr.: "A New Look at Logic Synthesis", Proceedings of 17th DAC, Minneapolis, pp.543-549 , 1980.

45
Darringer, J., Joyner, J.W., Berman, C., Trevillyan, L.: "Experiments in Logic Synthesis", Proc. IEEE Intern. Conf. on Circuits and Computers ICCC 80, pp.234-7A, 1980.

46
Darringer, J.A., Joyner, J.W., Berman, C., Trevillyan, L. : "Logic Syntesis Through Local Transformations", IBM J. of Res. and Devel. Vol. 25, no.4., July 1981.

47
Darringer, J.A., et al.: "LSS: A System for Production Logic Synthesis", IBM J. of Res. and Dev. vol 128, no.5, pp. 537-545, Sept. 1984.

48
DATA I/O "Product Guide, U.S. Edition, January 1985, DATA I/O, 10525 Willows Road N.E., P.O. Box 97046, Redmond, WA 98073-9746

49
Davis, W.A.: "Single Shift-Register Realization for Sequential Machines", IEEE Trans. on Comp., Vol 1-17, No. 5, pp. 421-431, May 1968.

50
Davidson, E.S.: "An Algorithm for NAND Decomposition Under Network Constraints", IEEE Trans. on Comp., Vol. C-18, pp. 1098-1109, 1969.

51
deGeus, A.J., Cohen, W.: "A Rule-Based System for Optimizing Combinational Logic", IEEE Design and Test, August 1985, pp.22-32.

52
De Michelli, G., Sangiovanni-Vincentelli, A., Villa, T.: "Computer-Aided Synthesis of PLA-Based Finite State Machines", Proc. IEEE 1983 Intern. Conf. on Computer Aided Design, pp. 154-156, September 1983.

53
De Micheli, G.: "Computer-Aided Synthesis of PLA-based Systems" Ph.D Dissertation, University of California, Berkeley 1983.

54
De Micheli, G., Santomauro, M.: "Topological Partitioning of Programmable Logic Arrays", Proc. of IEEE Intern, Conf. on Computer-Aided Design, pp. 182-183, Santa Clara , California 1983.

55
De Micheli, G., Brayton, R., Sangiovanni-Vincentelli, A.L.: "Optimal State Assignment for Finite State Machines" IBM Research Report RC 10599.

56
De Micheli, G., Hoffman, M., Newton, A.R., Sangiovanni-Vincentelli, A.L.: "A Design System for PLA-based Digital Circuits", in Advances in Computer Engineering Design, Jai Press, 1984

57
De Micheli, G.: "Optimal Encoding of Control Logic" Int. Conf. on Circ. and Comp. Des. Rye NY, Sept. 1984.

58
De Micheli, G. ,Brayton, R., Sangiovanni-Vincentelli, A.L.: "KISS: A Program for Optimal State Asignment of Finite State Machines" Int. Conf. on Comp. Aid. Design., Santa Clara, November 1984.

59
De Micheli, G., Brayton, R., Sangiovanni-Vincentelli, A.L.: "Optimal State Assignment for Finite State Machines". IEEE Transactions on Computer-Aided Design, Vol. CAD-4, No.3, pp. 269-285, July 1985.

60
De Micheli, G., Private communication.

61
De Micheli, G.: "Symbolic Minimization of Logic Functions", Proc. ICCAD 85, Santa Clara, California, pp.293-295, Nov.18-21, 1985.

62
Deschamps, J.P.: "Binary Simple Decomposition of Discrete Functions", Digital Processes, Vol. 1, pp. 123-140, 1975.

63
de Sarkar, S.C., Basu, A.K., Choudhury, A.K.: "Simplification of Incompletely Specified Flow Tables With the Help of Prime Closed Sets", IEEE Trans. Computers, Vol. C-18, pp.953-955, 19969.

64
de Sarkar, S.C., Basu, A.K., Choudhury, A.K.: "On the Determination of Irredundant Prime Closed Sets", IEEE Trans. Computers, Vol. C-20, pp.933-938, 1971.

65
Dietmeyer, D.L., Schneider, P.R.: "A Computer-Oriented Factoring Algorithm for NOR Logic Design", IEEE Trans. on Electr. Comp., Vol. EC-14, pp. 868-874, 1965.

66
Dietmeyer, D.L., Schneider, P.R.: "Identification of Symmetry, Redundancy and Equivalence of Boolean Functions", IEEE Trans. on Electr. Comp. , Vol. EC-16, pp. 804-817, December 1967.

67
Dietmeyer, D.L., Su, Y.H.: "Logic Design Automation of Fan-In Limited NAND Circuits", IEEE Trans. on Comp., Vol. C-18, pp. 11-22, 1969.

68
Dietmeyer, D.L.: "Logic Design of Digital Systems". Boston, Mass: Allyn and Bacon,1971.

69
Dolotta, T.A., McCluskey, E.G.: "The Coding of Internal States of Sequential Machines", IEEE Trans. Electr. Comp., Vol. EC-13, pp. 549-562, October 1964.

70
Doshi, M.S., Dietmeyer, D.C.: "Automated PLA Synthesis of DDL Descriptions", Univ. of Wisconsin at Madison Report, ECE 78-17, 1978.

71
Dunworth, A., Hartog, H.V.: "An Efficient State Minimization Algorithm for Some Special Classes of Incompletely Specified Sequential Machines", IEEE Trans. Comp., Vol. C-28, No. 7, p. 531-535, July 1979.

72
Dussault, J., Liaw, C.C., Tong M.:" A High Level Synthesis Tool for MOS Chip Design". Proc. 21-nd Design Automation Conf., Albuquerque, 25-27 June 1984.

73
ENDOT, Inc.: "Technical Data", ENDOT, Inc., 11001 Cedar Ave., Cleveland, Ohio, 44106.

74
Erdelyi, C.K., Griffin, W.R., Kilmoyer, R.D.: "Cascode Voltage Switch Design", VLSI Design, pp. 78-86, October 1984.

75
Floyd, R.W., Ullman, J.D.: "The Compilation of Regular Expressions into Integrated Circuits." JACM, Vol. 29., No.3, July 1982, pp. 603 - 622.

76
Foster, M.J.: "Specialized Silicon Compilers for Language Recognition", PhD Thesis, Department of Computer Science, Carnagie-Mellon University, July 1984.

77
Friedman, A.D., Menon, P.R.: "Theory and Design of Switching Circuits", Woodland Hills, California, Computer Science Press, Inc., 1975.

78
Friedman, N., Chandrasekhar, M.: "Area Efficient PLA's for Recognizing Regular Languages", Proc. 5-th Annual Intern. Conf. on Computers and Communications, pp.680-685, March 26-28, 1986, Scottsdale, Arizona.

79
Fritsnovich, G.F.: "Synthesis of a Microinstruction Decoder Using Programmable Logic Arrays", Avtomatika i Vychislitel'naya Tekhnika, Vol. 15, No.2, pp. 45-53, 1981.

80
Fujiwara, H.: "Logic Testing and Design for Testability", The MIT Press, 1985.

81
Garey, M.R., Johnson, D.S.: "Computers and Intractability. A Guide to the Theory of NP-Completeness", W.H. Freeeman and Company, San Francisco 1979.

82
Garrison, K., Gregory, D., Cohen, W., deGeus, A.: "Automatic Area and Performance Optimization of Combinatorial Logic", ICCAD 1984, pp.212-214, 1984.

83
Gilkinson, J.L., Lewis, S.D., Winter, B.R., Hekmatpour, A.: "Automated Technology Mapping", IBM J. Res. Develop. Vol. 28, no.5, September 1984.

84
Ginsburg, S.: "A Synthesis Technique for Minimal State Sequential Machines", IRE Trans. Electron. Computers, Vol. EC-8, No.1, pp.13-24, March 1959.

85
Ginsburg, S.: "On the Reduction of Superflous States in a Sequential Machine", J. Assoc. Computing Machinery, Vol.6., pp.259-282, April 1959.

86
Grasselli, A., Lucio, F.: "A Method of Minimizing the Number of Internal States in Incompletely Specified Sequential Networks", IEEE Trans. Electr. Comp., Vol. EC-14, No. 3, pp. 330-359, June 1965.

87
Gregory, D., Bartlett, K., deGeus, A.J.: "Automatic Generation of Combinatorial Logic from a Functional Specification", Proc. 1985 Int. Symp. on Circ. and Syst. Kyoto, Japan, June 1985.

88
Hallbauer, G.: "Procedures of State Reduction and Assignment in One Step in Synthesis of Asynchronous Sequential Circuits", Proc. Intern. IFAC Symp. on Discrete Systems, pp. 272-282, Riga, September 30 - October 4, 1974.

89
Hamachi, G.: "Peg Tutorial", VLSI Tools, Univ. of California, Berkeley, 1984.

90
Harel, D.: "Statecharts: A Visual Approach to Complex systems", Report, Dept. of Applied Math, The Weizmann Institute of Science, Rehovot, Israel, Dec. 1984.

91
Harrison, M.: "Introduction to Switching and Automata Theory", McGraw-Hill, New York, 1965.

92
Hartmanis, J.: "On the State Assignment Problem for Sequential Machines, I", IRE Trans. Electr. Comp., Vol. EC-10, pp. 157-165, June 1961.

93
Hartmanis, J., Stearns, R.E.: "Algebraic Structure Theory of Sequential Machines", Prentice-Hall, New York, 1966.

94
Hennie, F.C.: "Finite-State Models for Logical Machines", John Wiley, New York, 1968.

95
Hill, F.J., Peterson, G.R.: "Introduction to Switching Theory and Logical Design", 2nd Ed., New York, John Wiley & Sons, Inc., 1974.

96
Hoffman, M., Newton, R.: "A Synthesis System for CMOS Domino Logic", Proc. IEEE Int. Symp. Circuits and Systems, pp. 986-989, May 1984.

97
Hopcroft, J.E.: "An nlogn Algorithm for MInimizing States in a Finite Automaton", in Kohavi,Z., Paz, A. (eds), Theory of Machines and Computations, Academic Press, New York, pp. 189-196, 1971.

98
Hoshino, T., Endo, M., Karatsu, O.: "An Automatic Logic Synthesizer for Integrated VLSI Design System", Proc. 1984 Cust. Int. Circ. Conf., pp. 356-360, Rochester, NY, May 1984.

99
Hurson, A.R.: "A VLSI Design of the Parallel Finite State Automaton and its Performance Evaluation on a Hardware Scanner", Intl. J. of Comp. and Info. Science, Vol. 13, No. 5, pp. 481-505, 1984.

100
INTEL Solutions, March/April 1986, p.14.

101
Johnson, S.D.: "Synthesis of Digital Designs from Recursion Equations", The MIT Press, 1984.

102
Kabat, W.C. Wojcik, A.S.: "Automated Synthesis of Combinational Logic Using Theorem Proving Techniques", Proc. of the 12th Intern. Symp. on Multiple-valued Logic, Paris, May 1982, pp. 178 - 199.

103
Kalnberzin, A.Ya., Chapenko, V.P.: "Method of Input State Assignment for Digital Devices Implemented Using Programmable Logic Devices", Avtomatika i Vychislitel'naya Tekhnika, Vol. 17, No.1, pp. 41-47, 1983.

104
Kang, S.: "Synthesis and Optimization of Programmable Logic Arrays", Technical Report No 216, July 1981. Computer Systems Laboratory, Department of Electrical Engineering, Stanford University, 1981.

105
Karp, R.M.: "Functional Decomposition and Switching Circuit Design", J.SIAM, 1963.

106
Karp, R.M.: "Some Techniques of State Assignment for Synchronous Sequential Machines", IEEE Trans. Electr. Comp., Vol. EC-13, No. 5, pp. 507-518, October 1964.

107
Kella, J.: "State Minimization of Incompletely Specifed Sequential Machines", IEEE Trans. Computers, Vol. C-19, pp.342-348, 1970.

108
Kernighan, B.W., Lin , S.: "An Efficient Heuristic Procedure for Partitioning Graphs", Bell Syst. Tech. J. Vol.??, Feb. 1970, pp.291-307.

109
Kidson, D.: "A Consideration of the Use of Standard MSI Units in the Realization of Sequential Machines", Digital Processes, No. 4, pp. 85-107, 1978.

110
Kim, J.H., Siewiorek, D.P.: "Issues in IC Implementation of High Level, Abstract Designs", Proceedings of 17th DAC, Minneapolis, pp.85-91, 1980.

111
Kirkpatrick, S., Gelatt Jr, C.D., Vecchi, M.P.: "Optimizaton by Simulated Annealing", Science, Vol. 220, no. 4598, pp.671-680, 13 May 1983.

112
Klir, G.J.: "Introduction to the Methodology of Switching Circuits", D. Van Nostrand Co., New York , 1972.

113
Kohavi, Z.: "Secondary State Assignment for Sequential Machines" IEEE Trans. on Elect. Comp. pp. 193-203, June 1964.

114
Kohavi, Z.: "Switching and Finite Automata Theory", McGraw-Hill, New York, 1970.

115
Kowalski, T.J., Geiger, W.H., Wolf, W.H, Fichtner, W.: "The VLSI Design Automation Assistant: From Algorithms to Silicon", IEEE Design & Test, pp. 33-43, August 1985.

116
Krohn, K., Rhodes, J.L.: "Algebraic Structure Theory of Machines.I: the Decomposition Results", Trans. American Math Soc., CXVI 1965.

117
Lange ,E.E.: "Lower Bound For The Number of Terms in The System of DNF That Describes The Logical Structure of An Automaton" Avtomatika i Vychislitel'naya Tekhnika, Vol. 15, No.4, pp. 27-32, 1981.

118
Lawler ,E.L.: "An Approach to Multilevel Minimization", JACM, Vol. 11, No. 3, pp.283-295, July 1964.

119
Leive, G.W., Thomas, D.E.: "A Technology Relative Logic Synthesis and Module Selection System", Proc. 18th Design Automation Conf., June 1981, pp. 479-485.

120
Lee, H.P., Davidson, E.S.: "A Transform for NAND Network Design", IEEE Trans. on Comp. , Vol. C-21, N0.1, pp.12-20, January 1972.

121
Lee, E.B., Perkowski, M.: "A New Approach to Structural Synthesis of Automata". University of Minnesota, Department of Electrical Engineering, report, 1982.

122
Lee, E.B., Perkowski, M.: " Concurrent Minimization and State Assignment of Finite State Machines " . Proceedings of the 1984 Intern. Conf. on Systems, Man, and Cybernetics, IEEE, Halifax, Nova Scotia, Canada, October 9 - 12, 1984.

123
Lewin, D.: "Computer-Aided Design of Digital Systems", Crane Russak, New York, 1977.

124
Lucio, F.: "Extending the Definition of Prime Compatible Classes of States in Incomplete Sequential Machine Reduction", IEEE Trans. Computers, Vol. C-18, pp. 537-540, 1969.

125
Majorov, S.A.: "Design of Digital Computers" Energia, Leningrad 1972 (in Russian).

126
Meyer, M.J., Agraval, P., Pfister, R.G.: "A VLSI FSM Design System", Proc. 21sr Design Automation Conference, pp.434-440, Albuquerque, New Mexico, June 25-27, 1984.

127
Miller, R.E.: "Switching Theory. Vol. 1 + 2 ", John Wiley, New York 1965.

128
Moroz, D.Z.: "An Algorithm for Encoding the States of an Automaton", Avtomatika i Vychislitel'naya Tekhnika, Vol.4., No. 4, pp. 21-24, 1970.

129
Muller, D.E.: "Application of Boolean Algebra to Switching Circuit Design and Error Detection", IRE Trans. 1954, pp. 6-12.

130
Muroga, S., Ibaraki, T.: "Design of Optimal Switching Networks by Integer Programming", IEEE Trans. on Comp., Vol. C-21, pp. 573-582, June 1972.

131
Newton, A.R., Sangiovanni-Vincentelli, A.L.: "Computer-Aided Design for VLSI Circuits", Computer, April 1986, pp. 38 - 60.

132
Page, E.W, Marinos, P.N.: "Programmable Array Realizations of Synchronous Sequential Machines", IEEE Trans. on Computers, Vol.C-26, No.8, pp. 811-818. August 1977

133
Papachristou Ch. A., Sarma, D.: "An Approach to Sequential Circuit Construction in LSI Programmable Arrays", IEEE Proceedings, Vol. 130, Pt. E, No. 5, pp. 159-164, September 1983.

134
Paull, M.C., Unger, S.H.: "Minimizing the Number of States in Incompletely Specified Sequential Switching Functions," IEEE Trans. Electr. Comp. Vol. EC-8, 1959.

135
Parker, A.C., Thomas, D.E., Siewiorek, D.P., Barbacci, M., Hafer, L. Leive, G., Kim, J.: "The CMU Design Automation System - An Example of Automated Data Path Design", Proc. 16th Design Automation Conf., June 1979, pp. 73-80.

136
Perkowski, M.: "Synthesis of multioutput three level NAND networks". Proceedings of the Seminar on Computer Aided Design. Budapest, Hungary, 3-5 November 1976, pp. 238-265.

137
Perkowski, M.: "The state-space approach to the design of multipurpose problem-solver for logic design". Proceedings of the IFIP WG.5.2 Working Conference "Artificial Intelligence and Pattern Recognition in Computer-Aided Design". Grenoble, France, 17-19 March 1978, J. C. Latombe (ed.), North Holland, Amsterdam, pp. 124-140, 1978.

138
Perkowski, M.: "A System for Automatic Design of Digital Systems." Magyar Tudomanyos Akademia. Szamitastechnikai Es Automatizalesi Kutato Intezete. Budapest Tanulmanyok 99/1979 pp. 93-112. Hungary, 1979 (in Russian).

139
Perkowski, M.: "Automatischer Entwurf von MOS-LSI-digitalen Schaltungen in System DIADES". Messen, Steuern, Regeln, No. 6, 1979, pp. 346-350, East Germany, (in German).

140
Perkowski, M., Zasowska. A.,: "Minimal Area MOS Asynchronous Automata". Proceedings of the International Symposium on Applied Aspects of Automata Theory, Warna, Bulgaria, 14-19 May 1979, pp. 284-298.

141
Perkowski, M., Nguyen, N.: "Minimization of Finite State Machines in SuperPeg". Proceedings of the Midwest Symposium on Circuits and Systems. Luisville, Kentucky, 22-24 August 1985.

142
Perkowski, M.: "Systolic Architecture for the Logic Design Machine", Proc. Intern. Conference on Computer Aided Design, pp. 133-135, Santa Clara, November 1985.

143
Perkowski, M.: "A New Approach to the Structural Design of Finite State Machines", Department of EE, PSU, Report, 1986.

144
Perkowski, M, Smith, D., Krzywiec, R.: "Logic Simulation/Design/Verification Environment in Prolog", Proc. of 17th Annual Pittsburgh Conference on Modeling and Simulation, April 24-25, 1986.

145
Pfleger, C.F.: "Complete Sets and Time and Space Bounded Complexity", Doctoral Dissertation, Computer Science Dept., Pensylvania State Univ., University Park, PA 1974.

146
Ramamoorthy, C.V.: "Procedures for Minimization of "Exclusive-Or" and "Logical-Equivalence" Switching Circuits", Report.

147
Risch, R.H.: "Staggered Input Networks: An Approach to Automatic Logic Decomposition", Proc. of 1982 ISCAS Symp., Rome, pp.55-57, May 1982.

148
Roth, J.P.: "Computer Logic, Testing, and Verification", Computer Science Press, Potomac, MD., 1980.

149
Rowen, C. : "Multi-Level Logic Array Synthesis", Technical Report No. 85-279, Computer Systems Lab., Stanford University, July 1985.

150
Rudell, R.: "Finite State Machine Synthesis. State Assignment. Logic Minimization," Report, University of California, Berkeley, 1984.

151
Rudell, R.L., Sangiovanni-Vincentelli, A.L.: "Espresso-MV : Algorithms for Multiple-Valued Logic Minimization", IEEE 1985 Custom Integrated Circuits Conference, pp. 230-234.

152
Russo, G.V., Palama, G.: "Minimization of Incompletely Specified Finite State Machines", Digital Proceses, Vol. 6., pp. 199-206, 1980.

153
Russo, G.V., Palama, G., Neve, A.C.: "Really Prime Classes Implying only Really Prime Classes," Electr. Letters, Vol. 19, No. 13, 23 June 1983.

154
Sangiovanni-Vincentelli, A.L.: "An Overview of Synthesis Systems", Proc. IEEE 1985 Custom Integrated Circuits Conference, pp.221-225, May 1985.

155
Sasao, T.: "An Algorithm to Derive the Complement of a Binary Function with Multiple-valued Input", IEEE Trans. on Comput., Vol. C-34, No.2, pp.131-140, Febr. 1985.

156
Sasao, R.: "HART: A Hardware for Logic Minimization and Verification", IEEE Proc. of the Intern. Conf. on Computer Design: VLSI in Computer, October 7-10, 1985, Port Chester, NY.

157
Saucier, G.: "State Assignment of Asynchronous Sequential Machines Using Graph Techniques", IEEE Trans. on Comp. Vol. C-21, pp. 282-288, March 1972.

158
Schmidt, D.C., Metze, G.: "Modular Replacement of Combinational Switching Networks", IEEE Trans. on Comp., Vol. C-24, pp. 29-48, 1975.

159
Shahdad, M.: "An Overview of VHDL Language and Technology", Proc. of the 23-rd Design Automation Conference, ACM and IEEE, Las Vegas, pp. 320-326, June 29- July 2, 1986.

160
Shen, V., Mc Kellar, A.: "An Algorithm for the Disjunctive Decomposition of Switching Functions", IEEE Trans. on Comp. Vol. C-19, pp. 239-248, 1970.

161
Shen, V., Mc Kellar, A.: "A Fast Algorithm for the Disjunctive Decomposition of Switching Functions", IEEE Trans. on Comp. Vol. C-20, pp. 304-309, 1971.

162
Shinsha, T., et al.: "POLARIS: Polarity Propagation Algorithm For Combinational Logic Synthesis", 21st Design Automation Conference, IEEE 1984.

163
Shirakawa, I., Okuda, N., Harada, T., Tani, S., Ozaki, H.: "A Layout System for Random Logic Portion of MOS LSI", Proceedings of 17th DAC, Minneapolis, pp.92-99 , 1980.

164
Shiva, S.G.: "Combinational Logic Synthesis from HDL Description", Proceedings of 17th DAC, Minneapolis, pp. 550-555 , 1980.

165
Sinha Roy, P.K., Sheng, C.L.: "A Decomposition Method of Determining Maximum Compatibles", IEEE Trans. Computers, Vol. C-21, pp.309-312, 1972.

166
Sklyarov, V.A.: "Design of Automata Using Programmable Logic Arrays with Memory", Kibernetika, pp.840-848, Plenum Publishing Corp., 1985.

167
Southard, J.R., Domic, A., Crouch, K.W.: "Report on the Lincoln Boolean Synthesizer", Digest of ICCAD , pp.192-193, IEEE, September 1983. Springer Verlag, Berlin-New York, 1981.

168
Stearns, R.E., Hartmanis, J.: "On the State Assignment Problem for Sequential Machines, II", IRE Trans. Electr. Comp., Vol. EC-10, No. 4, pp. 593-603, December 1961.

169
Stentiford, F.W.H., Lewin, D.W.: "Heuristic Procedure for Reduction of Finite-State Machines", IEE Electron. Lett., Vol.7, pp.700-702, 1971.

170
Story, J.R., Harrison, H.J., Reinhard, E.A.: "Optimum State Assignment for Synchronous Sequential Circuits", IEEE Trans. on Comp., Vol. C-21, No. 12, pp. 1365-1373, December 1972.

171
Su, S.Y.H., Nam, C.W.: "Computer Aided Synthesis of Multiple Output Multilevel NAND Networks With Fan-In and Fan-Out Constraints", IEEE Trans. on Comp., Vol. C-20, pp. 1445-1455, 1971.

172
Supovit, K., Friedman, S.J.: "A New Method for Verifying Sequential Circuits", Proc. 23rd Design Automation Conf., pp. 200-207, June 29-July 2, Las Vegas 1986.

173
Svoboda, A.: "Advanced Logical Circuit Design Techniques", Garland STMP Press, New York, 1979.

174
Teel, B., Wilde, D.: "A Logic Minimizer for VLSI PLA Design", Proc 19-th Design Automation Conference, ACM-IEEE, June 1982.

175
Thayse, A.: "A Fast Algorithm for Proper Decomposition of Boolean Functions", Philips Res. Rep. No. 27, pp. 140-150, 1972.

176
Torng, H.C.: "Introduction to the Logical Design of Switching Systems," Addison-Wesley, Reading, Massachusetts, 1964.

177
Torng, H.C.: "An Algorithm for Finding Secondary Assignments of Synchronous Sequential Circuits", IEEE Trans. on Comp. Vol. C-17, pp. 416-469, May 1968.

178
Tracey, J.H.: "Internal State Assignment for Asynchronous Machines" IEEE Trans on Electr. Comp. Vol. EC-15, pp. 551-560, August 1966.

179
Vavilov, E.N., Portnoy, G.P.: "Synthesis of Circuits of Electronic Computers," Energia Publishers, Moscov, 1966 (in Russian).

180
Wieclawski, A., Perkowski, M.: " Optimization of Negative Gate Networks Realized in Weinberger-like layout in a Boolean Level Silicon Compiler". Proceedings of 21st Design Automation Conference, ACM and IEEE, Albuquerque, 25 - 27 June, 1984.

181
Wieclawski, A., M. Perkowski.: "Optimization of Negative Gate Networks," Department of Electrical Engineering, Portland State University, Technical Report, version 2, May 1984.

182
Weiner, P., Smith, E.J.: "Optimization of Reduced Dependencies for Synchronous Sequential Machines", IEEE Trans. on Electr. Comp., Vol. EC-16, pp. 835-847, December 1967.

183
Viewlogic Systems, Inc: "WorkView", 33 Boston Post Road, West Marlboro MA 01752, 1986.

184
Yang, C.: "Closure Partition Method for Minimizing Incomplete Sequential Machines", IEEE Trans. Computers, Vol. C-29, No.8, pp. 732-736, August 1980.

185
Yamamoto, M.: "A Method for Minimizing Incompletely Specified Sequential Machines," IEEE Trans. Comp. Vol C-29, No. 8, pp. 732-736, August 1980.

186
Zakrevskij, A.A.: "Algorithms of Discrete Automata Synthesis", Nauka, Moscow, 1971 (in Russian).

187
Zasowska, A., Perkowski, M.: "The Computer-Oriented Method for Joint Minimization and State-Assignment of Synchronous and Asynchronous Automata", Proc. of the Conf., "Application of Computers in Engineering Design", Katowice, Poland, 1979.

188
Zeiger, H.P.: "Cascade Decomposition of Automata using Covers", In the Algebraic Theory of Machines, Languages, and Semigroups, by M.A. Arlib, Academic Press, Netherlands, 1968.

189
Zhang, Y.Z., Rayner, P.J.W.: "Minimisation of Reed-Muller Polynomials with Fixed Polarity", IEE Proceedings, Vol. 131, Pt.E, No. 5, September 1984.


Marek Perkowski
Tue Nov 11 20:04:24 PST 1997