BACK TO MAIN PAGE OF Professor Marek Perkowski.
Our standard class meetings are in room EB 103, Mondays, Wednesdays 1:00-3:20pm.
My email is mperkows@ee.pdx.edu.
Our additional meetings are in room FAB 150, Fridays 5-7pm.
Ms Sophie Choe, the class TA and grader has her office hours on Thursdays, 4:00- 6:00 in room 100.
Her email is sophchoe@pdx.edu . PLEASE USE THIS OPORTUNITY TO LEARN MORE.
TEXTBOOK: John F. Wakerly. Digital Design. Principles and Practices. Fourth Edition.
Remember, that the main reading material is the Wakerly's Book. You can learn, however, all material from class slides only.
This book will be used in ECE 271 as well. So it is worthy to purchase.
The material given below is only auxiliary, to help you extend knowledge from the book.
How to learn for this class.
This class includes much material and is fast paced.
You have to read the mandatory slides before each lecture.
If I have no time to complete the slides, you are supposed to read this material on your own.
Do not read the book linearly. Read the material that you need to understand slides in full detail.
If you read both the book and my slides carefully
and you are able to solve the problems that you can find in this webpage,
then do not worry about your grade.
FOR YEAR 2017. MANDATORY LECTURES FOR THE ECE 171 CLASS TAUGHT BY DR. MAREK A. PERKOWSKI
The schedule of the meetings may change.
The class is graded on Midterm, homeworks and projects and final. There are no unexpected quizzes this year.
There is only one Midterm.
MEETING 1
- Lecture1 Number Systems.pptx
- TOPICS: Class introduction. Radix number representation. Binary, octal, hexadecimal. Fixed point numbers. Radix conversions.
- TOPICS: Explanation of my webpage, password and how to use the page.
- ASSIGNMENTS. Read Administration and Syllabus on this web site.
- ASSIGNMENTS. Read Wakerly. Sections 1.1 - 1.2 2.1 - 2.3.
- HOMEWORK. due xxx
MEETING 2
- Lecture2 Binary Arithmetics.pptx
- TOPICS: Representing negative numbers. Sign/magnitude. Ones complement. Binary addition, subtraction, overflow. Sign extension.
- ASSIGNMENTS. Read Wakerly, Sections 2.4 - 2.6.
- HOMEWORK. due xxx
MEETING 3
- Lecture3 Floating Point and Codes.pptx
- TOPICS: IEEE 754 Floating Point Standard. BCD, ASCII, Gray 754 Floating Point Standard.
- TOPICS: Seven segment display code.
- TOPICS: one-hot and m-out-of-n codes. Serial line codes.
- ASSIGNMENTS. Read Wakerly, Sections 2.10-2.12, 2.15.7, 2.16.
- HOMEWORK. due xxx
MEETING 4
- Lecture4 Boolean Algebra.pptx
- TOPICS: Boolean Algebra. Huntington's postulates. Truth Tables, schematic symbols.
- ASSIGNMENTS. Read Wakerly, Section 4.1.
- HOMEWORK. due xxx
MEETING 5
- Lecture5 Boolean Equations and KMaps.pptx
- TOPICS: Canonical Sum of Products form. Product of Sums form.
Compact minterm and maxterm forms. Logic Minimization in Karnaugh Maps. Product term sharing.
- ASSIGNMENTS. Read Wakerly, Section 4.3.
- HOMEWORK. due xxx
MEETING 6
- Lecture6 Symbols, Analysis, Design, NANDs.pptx
- TOPICS: Schematic symbols. Switching circuits. Schematic diagrams. Equivalent symbols.
NAND/NAND and NOR/NOR implementation.
- ASSIGNMENTS. Read Wakerly, Sections
3.1-3.3, 3.3.2- 3.3.4, 4.2, 6.1.2.
- HOMEWORK. due xxx
MEETING 7
- Lecture7 Integrated Circuits.pptx
- TOPICS: Implementing logic. Integrated circuits. Printed Circuit Boards.
Logic families. Datasheets.
- ASSIGNMENTS. Read Wakerly, Sections 1.6-1.9, 4.3.1 - 4.3.2. 3.4.
- HOMEWORK. due xxx
MEETING 8
- Lecture8 Verilog.pptx
- TOPICS: Hardware Description Languages. Verilog. Dataflow Descriptions.
- ASSIGNMENTS. Read Wakerly, Sections 5.1, 5.4.1-5.4.6, 5.4.8, 5.4.11 - 5.4.13.
- PROJECT. due xxx
- EXAMPLE PROJECT SOLUTION.
MEETING 9. MIDTERM
- Covers all material to present except VERILOG. Open Book. Open Notes. No computers, calculators, phones or other devices.
- Bring ASCII chart/table.
MEETING 10
- More Verilog.
- TOPICS: Structural descriptions. Testbench techniques. Timing Diagrams. Midterm Exam solutions.
- TOPICS: Midterm Exam solutions.
- ASSIGNMENTS. Read Wakerly, Sections 5.4.7, 5.4.9.
MEETING 11
- Lecture 9 Hazards Decoders Multiplexers.pptx
- TOPICS: Glitches and Hazards. Static and Dynamic Hazards. Avoiding dynamic hazards, eliminating logic hazards. Decoders and Multiplexers.
Universal function implementers.
- ASSIGNMENTS. Read Wakerly, Sections 4.4, 6.4.1, 6.7.1.
- HOMEWORK. due xxx
MEETING 12
- Lecture 10 ROM PLA PAL PLD.pptx
- TOPICS: PLA, PROM, PAL, GAL. CPLDs.
- ASSIGNMENTS. Read Wakerly, Sections 6.3.1 - 6.3.4.
- HOMEWORK. due xxx
MEETING 13.
- Lecture 11 Blocks Decoders Demux.pptx
- TOPICS: Open Collector, Open Drain, Tri-state Outputs. Tri-state buffers. Bus outputs. Multiplexers.
- TOPICS: Decoders. XOR and XNOR. Parity.
- ASSIGNMENTS. Read Wakerly, Sections 3.7.3-3.7.7, 6.6.1, 6.7.3, 6.8.1, 6.8.2, 6,8,4.
- PROJECT 2. Testbench for Project 2.
MEETING 14.
- Lecture12 Adders Multipliers.pptx
- TOPICS: Modular design. Half adders. Full adders. Subtractors.
- ASSIGNMENTS. Read Wakerly, Sections 6.10.1.
- HOMEWORK. due xxx
MEETING 15.
- Ripple Carry Adders.
- Carry Lookahead Adders.
- ASSIGNMENTS. Read Wakerly, Sections 6.10.2, 6.10.4.
- HOMEWORK. due xxx
MEETING 16.
- TOPICS: Multipliers. ALU design.
- ASSIGNMENTS. Read Wakerly, Sections 6.10.6.
- HOMEWORK. due xxx
MEETING 17.
- Lecture 13 State Machines.pptx
- TOPICS: Latches. Flip-flops. Clocks. State Machines. State Transition Diagrams.
- TOPICS: PS/NS stables. Counters.
- ASSIGNMENTS. Read Wakerly, Sections 7.2.1 - 7.2.6, 7.2.10 - 7.2.11, 7.3.
- HOMEWORK. due xxx
MEETING 18.
- TOPICS: Review of State Machines.
- ASSIGNMENTS. Read Wakerly, Section 7.5.
MEETING 19.
- TOPICS: Review before Final Exam. All material.
MEETING 20. FINAL EXAM.
- Comprehensive. Covers all material except Verilog.
- Open Book. Open notes.
- No computers or phones.
- Bring 74HCT08 datasheet.
- Bring Scantron Form 882-E (available in PSU bookstore).
WARNING.
MATERIAL BELOW THIS LINE IS NOT MANDATORY.
WARNING.
MATERIAL BELOW THIS LINE IS NOT MANDATORY.
IT IS ADDED JUST TO HELP YOU BEING ABLE TO BETTER SOLVE MORE ADVANCED PROBLEMS.
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##### REVIEW MATERIAL FOR MIDTERM. #####
- Most Important Material for Midterm.
- Use of Kmaps and logic design.
- Boolean Laws and how to use them. Laws of EXOR logic and Boolean Algebra. De Morgan Rules.
- Synthesis of multiple-output circuits. Common functions.
- Factorization and synthesis of multi-level circuts. Cost of gates - number of inputs to gates.
USEFUL TOOLS FOR PROBLEM SOLVING:
- blank_kmaps.pdf
This is a collection of Kmaps. Print it and copy. Use in homeworks, projects and exams.
- cheat_sheet.pdf
This is a cheat sheet. Use it in quizzes,homeworks, projects and exams.
Material on Combinational Logic and circuits to be covered in Midterm.
- Review of Karnaugh Maps: variables, literals, products, product implicants, Prime implicants, essential prime implicants.
- How to draw a Kmap.
- Finding good groups in a Kmap.
- Covering problem of minterms in Kmap.
- Various uses of Kmaps to design with Muxes.
- Analysis methods (based on Kmaps, netlists, expressions).
- The importance of good selection of the analysis method.
- The relations between analysis and synthesis.
- NAND and NOR gates. Their use.
- Incompletely specified functions.
- Complete sets of gates, examples: NAND, NOR, AND/OR/NOT, AND/EXOR/1.
- Simple methods of EXOR-based synthesis by Kmap methods.
- Factorization of multi-output functions.
- Inhibition methods that use NAND and NOR gates.
- There will be additional points given for solving the problems.
CHALLENGE PROBLEM 1. VERY DIFFICULT. 20 points.
Given are two inverters and any number of two-input gates OR and AND. Other gates are not allowed.
Realize the function A = NOT(a), B = NOT(b), C = NOT(c).
PROBLEM 2. QUITE EASY. 5 points.
Given is arbitrary graph with 4 nodes and 5 edges. The encoding of colors is : red=00, blue=01, yellow=11, green=10.
Design a combinational circuits, called the oracle, that will give 1 on output for every good coloring. Show all gates. Draw schematics for your given graph.
How to exercise this oracle? How to give all binary inputs to it? Write software or pseudo-code. Show all solutions.
Challenge problems will be given for those of you who
enjoy creativity and problem solving and to find potential candidates for individual undergraduate honor work - research on new topics and study of new research areas.
- ADDITIONAL MATERIAL, NOT REQUIRED: Lecture about BDD and multiplexers in synthesis.
The knowledge about BDD is not mandatory.
The knowledge about pass transitor and CMOS logic is additional and will be not required on tests.
- Designing with MUX and gates. Expanding functions with respect to subsets of variables.
- Various patters of control variables on a Kmap.
- Use of MUXes for hierarchical decomposition.
- Combining various logic synthesis methods.
Material on FSMs and Sequential circuits to be covered in Final.
- Latches.
- Flip-Flops.
- Synchronous Devices.
- Designing binary counters.
- Designing sequential parity checkers.
- Please look to data sheets at the bottom of this page for practical examples of logic and
sequential blocks, components, counters, etc.
- Read about sequential parity checkers.
- The notations used for state machines.
- Moore and Mealy machines, examples.
- Review of the basic method to calculate the excitation functions for Mealy machines.
- Timing analysis of Mealy machine.
- Review of Shifters.
- Analysis of autonomous FSM.
- Analysis of non-autonomous FSM: from schematic to state machine graph.
- Review of sequential parity checkers.
- Schematics of Finite State Machines and their analysis.
- FSMs as sequence transformers, acceptors and generators, time analysis.
- Solve three arbitrary problems that have solutions and check them.
- Design of counters with large sequences.
- Systematic Procedures for designing state machines with D, T and JK flip-flops.
- Method with bold symbols. Selection of the best flip-flop.
- Designing a flip-flop from another flip-flop.
- Review on generalized registers: combining generalized registers with counters and adders.
- Systematic versus ad hoc methods for designing state machines.
- Design of sequence acceptors and sequence generators.
- Register transfer using Shift registers.
- Arithmetic and logic operations using Shift registers.
- Relations between state machines and iterative circuits.
- The need for verification. Verification methods: graphical versus symbolic.
- Shift registers and Johnson Counters.
PROBLEMS FROM WAKERLY'S BOOK WITH SOLUTIONS.
Some of you ask for solutions to Wakerly problems.
I do not think that all are available. Here are all solutions to Wakerly that I have.
For more problems with solutions look to my lectures from this webpage below.
You should read all "Mandatory" lecture slides, but additional and auxiliary slides include many good problems to solve.
- Problems to chapter 4. Combinational Circuits.
- Problems to chapter 5. Combinational Circuits.
- Problems to chapter 7. Sequential Circuits.
- Problems to chapter 8. Sequential Circuits.
##### EXAM PROBLEMS ON COMBINATIONAL CIRCUITS. #####
This section includes typical problems on combinational circuits.
The slides below were added for your request.
-
Karnaugh Maps and their use - problems to solve.
-
002. Examples to Midterm 1 - Kmaps and their uses - easy.ppt
-
003. Examples to Midterm 1 - Advanced Minimization,Kmaps - EXOR - factorization.ppt
-
004. Examples to Midterm 1 - Problems SOP.ppt
-
005. Examples to Midterm 1. Problems. Multi-output SOP.ppt
-
006. Examples to Midterm 1 - multi-level logic.ppt
-
007. Examples to Midterm 1 - Multi-level synthesis from various gates.ppt
-
008. Examples to Midterm 1 - Iterative circuits-mux-adders.ppt
-
009. Examples to Midterm 1 = Problems- adders and seven segment displays.ppt
-
010. Examples to Midterm 1 - Mux demultiplexers and ROMs.ppt
-
012. Examples to Midterm 1 - problems from Hintz.ppt
- Midterm 1 in last year.
- Big selection of mostly easy Problems for Midterm 1.
- Design of comparator and multiplier.