--VHDL code for move object--
-- Autogram To VHDL code generator $Revision: 1.15 $
-- generated from autogram "mvo.AUT"
-- Generator Flags
-- Comments On
-- Type std_logic
-- Synchronous Reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mvo IS
PORT (
a : IN std_logic;
b : IN std_logic;
c8 : IN std_logic;
c7 : IN std_logic;
c6 : IN std_logic;
c5 : IN std_logic;
c4 : IN std_logic;
hm : IN std_logic;
Bcc : OUT std_logic;
Shd : OUT std_logic;
Eld : OUT std_logic;
Grc : OUT std_logic;
Elu : OUT std_logic;
Gro : OUT std_logic;
Ghm : OUT std_logic;
res : OUT std_logic;
clock : IN std_logic);
END mvo ;
ARCHITECTURE autogram OF mvo IS
TYPE autogram_current_type IS (
state0,
state1,
state2,
state3) ;
SIGNAL autogram_current : autogram_current_type:= state0;
SIGNAL autogram_next : autogram_current_type:= state0;
SIGNAL autogram_reset : std_logic;
BEGIN
synchronous:
PROCESS(clock)
BEGIN
IF (clock='1' AND clock'event) THEN
autogram_current <= autogram_next;
END IF ;
END PROCESS synchronous;
asynchronous:
PROCESS(autogram_current,a,b,c8,c7,c6,c5,c4,hm)
BEGIN
-- Default signal values are inactive
Bcc <= '0';
Shd <= '0';
Eld <= '0';
Grc <= '0';
Elu <= '0';
Gro <= '0';
Ghm <= '0';
res <= '0';
CASE autogram_current IS
WHEN state0 =>
-- autogram line 2
IF ( ( a AND b ) = '1' ) THEN
autogram_next <= state1;
END IF ;
WHEN state1 =>
-- autogram line 3
IF ( ( NOT c8 AND NOT c7 AND NOT c6 ) = '1' ) THEN
Bcc <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 4
IF ( ( NOT c8 AND NOT c7 AND c6 ) = '1' ) THEN
Shd <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 5
IF ( ( NOT c8 AND c7 ) = '1' ) THEN
Eld <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 6
IF ( ( c8 AND NOT c7 AND NOT c6 AND NOT c5 AND NOT c4 ) = '1' ) THEN
Grc <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 7
IF ( ( c8 AND NOT c7 AND NOT c6 AND NOT c5 AND c4 ) = '1' ) THEN
Elu <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 8
IF ( ( c8 AND NOT c7 AND NOT c6 AND c5 AND NOT c4 ) = '1' ) THEN
Bcc <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 9
IF ( ( c8 AND NOT c7 AND NOT c6 AND c5 AND c4 ) = '1' ) THEN
Eld <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 10
IF ( ( c8 AND NOT c7 AND c6 AND NOT c5 AND NOT c4 ) = '1' ) THEN
Gro <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 11
IF ( ( c8 AND NOT c7 AND c6 AND NOT c5 AND c4 ) = '1' ) THEN
Elu <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 12
IF ( ( c8 AND NOT c7 AND c6 AND c5 ) = '1' ) THEN
autogram_next <= state2;
END IF ;
WHEN state2 =>
-- autogram line 13
IF ( ( NOT hm ) = '1' ) THEN
Ghm <= '1';
autogram_next <= state2;
END IF ;
-- autogram line 14
IF ( ( hm ) = '1' ) THEN
autogram_next <= state3;
END IF ;
WHEN state3 =>
res <= '1';
IF ( ( NOT a OR NOT b ) = '1' ) THEN
autogram_next <= state0;
END IF;
END CASE ;
END PROCESS asynchronous;
END autogram;
--VHDL code for go-home--
-- Autogram To VHDL code generator $Revision: 1.15 $
-- generated from autogram "ghmvhd.AUT"
-- Generator Flags
-- Comments On
-- Type std_logic
-- Synchronous Reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ghm IS
PORT (
GoHm : IN std_logic;
Bhm : IN std_logic;
Shm : IN std_logic;
Ehm : IN std_logic;
Ghm : IN std_logic;
Whm : IN std_logic;
Bcw : OUT std_logic;
Shu : OUT std_logic;
Elu : OUT std_logic;
Gro : OUT std_logic;
Wcw : OUT std_logic;
Hm : OUT std_logic;
clock : IN std_logic);
END ghm ;
ARCHITECTURE autogram OF ghm IS
TYPE autogram_current_type IS (
state0,
state1,
state2) ;
SIGNAL autogram_current : autogram_current_type:= state0;
SIGNAL autogram_next : autogram_current_type:= state0;
BEGIN
synchronous:
PROCESS(clock)
BEGIN
IF (clock='1' AND clock'event) THEN
autogram_current <= autogram_next;
END IF ;
END PROCESS synchronous;
asynchronous:
PROCESS(autogram_current,GoHm,Bhm,Shm,Ehm,Ghm,Whm)
BEGIN
-- Default signal values are inactive
Bcw <= '0';
Shu <= '0';
Elu <= '0';
Gro <= '0';
Wcw <= '0';
Hm <= '0';
CASE autogram_current IS
WHEN state0 =>
-- autogram line 2
IF ( ( NOT GoHm ) = '1' ) THEN
autogram_next <= state0;
END IF ;
-- autogram line 3
IF ( ( GoHm ) = '1' ) THEN
autogram_next <= state1;
END IF ;
WHEN state1 =>
-- autogram line 4
IF ( ( NOT Bhm ) = '1' ) THEN
Bcw <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 5
IF ( ( NOT Shm ) = '1' ) THEN
Shu <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 6
IF ( ( NOT Ehm ) = '1' ) THEN
Elu <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 7
IF ( ( NOT Ghm ) = '1' ) THEN
Gro <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 8
IF ( ( NOT Whm ) = '1' ) THEN
Wcw <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 9
IF ( ( Bhm AND Shm AND Ehm AND Ghm ) = '1' ) THEN
autogram_next <= state2;
END IF ;
WHEN state2 =>
Hm <= '1';
-- autogram line 10
IF ( ( GoHm ) = '1' ) THEN
autogram_next <= state2;
END IF ;
-- autogram line 11
IF ( ( NOT GoHm ) = '1' ) THEN
autogram_next <= state0;
END IF ;
END CASE ;
END PROCESS asynchronous;
END autogram;
--VHDL code for danger
-- Autogram To VHDL code generator $Revision: 1.15 $
-- generated from autogram "dng.AUT"
-- Generator Flags
-- Comments On
-- Type bit
-- Synchronous Reset
ENTITY dng IS
PORT (
a : IN bit;
b : IN bit;
c5 : IN bit;
c4 : IN bit;
Grc : OUT bit;
Gro : OUT bit;
Wcc : OUT bit;
Wcw : OUT bit;
res : OUT bit;
clock : IN bit);
END dng ;
ARCHITECTURE autogram OF dng IS
TYPE autogram_current_type IS (
state0,
state1,
state2) ;
SIGNAL autogram_current : autogram_current_type:= state0;
SIGNAL autogram_next : autogram_current_type:= state0;
BEGIN
synchronous:
PROCESS(clock)
BEGIN
IF (clock='1' AND clock'event) THEN
autogram_current <= autogram_next;
END IF ;
END PROCESS synchronous;
asynchronous:
PROCESS(autogram_current,a,b,c5,c4)
BEGIN
-- Default signal values are inactive
Grc <= '0';
Gro <= '0';
Wcc <= '0';
Wcw <= '0';
res <= '0';
CASE autogram_current IS
WHEN state0 =>
-- autogram line 2
IF ( ( a AND NOT b ) = '1' ) THEN
autogram_next <= state1;
END IF ;
WHEN state1 =>
-- autogram line 3 and 4
IF ( ( NOT c5 AND NOT c4 ) = '1' ) THEN
Grc <= '1';
Wcc <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 5 and 6
IF ( ( NOT c5 AND c4 ) = '1' ) THEN
Gro <= '1';
Wcw <= '1';
autogram_next <= state1;
END IF ;
-- autogram line 7
IF ( ( c5 AND NOT c4) = '1' ) THEN
autogram_next <= state2;
END IF ;
WHEN state2 =>
res <= '1';
IF ( ( NOT a OR b ) = '1' ) THEN
autogram_next <= state0;
END IF;
END CASE;
END PROCESS asynchronous;
END autogram;
--