1. This is only a very short introduction to problems that may be on the final.
   
2. Problem 1.
   Test generation.
   1. Given is a function F(a,b,c,d) given as a Karnaugh map.
   2. Fault model are faults stuck-at-0 and stuck-at-1 in any wire.
   3. Assume any given wire x to be a stuck-at-0 or stuck-at-1 fault and draw the network with the fault.
      For instance, assuming s-a-1 fault in wire X you create function F_X_s_a_1.
      Assuming s-a-0 fault in input a you create function F_a_s_a_1.
   4. Draw a Karnaugh map for the function with this fault inserted.
   5. Perform the EXOR operation on the fault table and the correct table to find all tests for this fault.
   6. Repeat for any fault assumed.
   7. Write the set of tests for your set of faults.
   
   
3. Problem 2.
   Minimum set of tests.
   1. Given is a function F(a,b,c,d) given as a Karnaugh map.
   2. Fault model are faults stuck-at-0 and stuck-at-1 in any wire.
   3. Assume any given wire x to be a stuck-at-0 or stuck-at-1 fault and draw the network with the fault.
   4. As in problem 1, assume some finite set of faults and find all possible tests for each fault.
   5. Create a table with faults as columns and tests as rows.
   6. Find the minimum number of tests for all faults solving the covering problem.
   
   
4. Problem 3.
   Testing a sequential circuit.
   1. Given is a circuit with one input, one output and two D-type flip-flops.
   2. The output function is: Y = Q1 * Q2.
   3. The excitation functions are: D1 = x Q2 + x' Q1.
   4. D2 = x Q1 Q2' + x' Q2 Q1'.
   5. Draw the SCAN circuit with Muxes that allows to shift in any test sequence from the additional input TEST_IN.
   6. Write the test sequence for detecting all faults stuck-at-1 in x, Y, Q1 and Q2. Try to minimize its length.
   7. Describe in detail how the test is performed, specify sequence of signals and what happens.
   8. Design a random test generator for this example.
   9. Design the MISR circuit for this example.
   10. Explain self test on this example.