CLASS SCHEDULE

MONDAY, SEPTEMBER 27, 1999

1. Introduction to class. Grading system.
   There will be experimentally three grading options:
   OPTION 1: 100 % on Exams and Homeworks.
   OPTION 2: 100 % on Projects.
   OPTION 3: 50 % on Exams and Homeworks, 50 % on Projects.
   Projects for Ph.D. and M.S. students will be more complex and/or ambitious. For Ph.D, publication quality research is a goal.
2. General Plan:
   1. Introduction to binary logic and digital design. Review.
   2. Realization Technologies of Digital Logic. Requirements for design: power, area, speed, testability.
   3. Boolean and Multiple-Valued Functions: Characterization, Types and Operators.
   4. Representation of Boolean and Multiple-Valued Functions: Cube Calculus, Decision Diagrams, Labeled Rough Partitions.
   5. Basic Combinatorial Algorithms: Set Covering (Unate Covering), Covering/Closure (Binate Covering), Graph Coloring, Maximum Clique, Shortest Path, Longest Path, Maximu Flow, etc.
   6. Two Level Minimization.
   7. Minimization of functions with few levels.
   8. Multi-level Minimization: Factorization and BDD-based methods.
   9. Spectral Approaches: Walsh, Hadamard, Haar, Fourier, Reed-Muller.
   10. Reed-Muller Logic.
   11. EXOR Circuits.
   12. Linearly-Independent Logic: application in image processing.
   13. Decomposition.
   14. Implicit Methods.
   15. Low Power Design.
   16. Overview of recent methods and theories.
3. LECTURE
4. Review of Basic Logic Design and Boolean Algebra.

   WEDNESDAY, SEPTEMBER 29, 1999.

   1. LECTURE
   2. Functions, relations, sets of functions, sets of relations.
   3. Tabular representation of functions and relations.
   4. Cube Calculus representation of functions and relations.
   5. Introduction to symmetric functions and their representation.
   6. Introduction to EXOR logic. Reasons of interest in it, applications.
   7. Basic formulas for EXOR logic.
   8. Shannon, Positive and Negative Davio expansions. SOP and Positive Davio (Reed-Muller) Canonical forms.
   9. Shannon Trees, Positive Davio Trees.
   10. Flattening of Trees to canonical forms. Decision Diagrams.

   MONDAY, OCTOBER 4, 1999

   1. LECTURE
   2. Continuation on SOP, multiple-output functions.
   3. EPLDs and FPGAs.
   4. Continuation on Binary Decision Diagrams and Kronecker Decision Diagrams.
   5. EXOR canonical forms for representation and synthesis.
      

   WEDNESDAY, OCTOBER 6, 1999

   1. LECTURE
   2. Number Systems
   3. Arithmetic Circuits.
   4. Adder, Subtracter, Carry-Look-Ahead ideas.
   5. ALUs and multipliers.
   6. Sequential versus combinational circuits.
   7. Introductionto Iterative Circuits.
   8. Homework 1.
      1. Design an arbitrary function of 4 or 5 variables that is quite complex.
      2. Show Kmap and BDD for it for two orders of variables.
      3. Discuss the role of variable ordering.
      4. Show all stages of your work.
   9. Homework 2.
      1. Create an example of a function with more than 3 outputs and not less than 4 inputs, for which the minimum cost function realization cannot be found by minimizing each function separately.
      2. Derive the minimum solution, use Petrick function, branching method or any other method that PROVES that your design has the minimum cost.
      3. Compare with the solution based on minimizing EXACTLY each function SEPARATELY.
      4. Show all your stages in detail.
   10. BOTH HOMEWORKS REQUIRE TO USE POWER POINT.
   11. NEXT COMPILE TO HTML AND CREATE YOUR OWN WWW PAGE.
   12. SEND ME THE EMAIL WITH THE HTTP ADDRESS OF THIS PAGE.

   MONDAY, OCTOBER 11, 1999

   1. Typical stages of a complete design automation system.
   2. Top-Down versus Bottom-Up versus Middle-Outside methodologies.
   3. Latches and Flip-Flops.
   4. Transition tables, excitation tables and FSM specifications.
   5. Homework 3.
      1. Design bottom-up a state machine from arbitrary gates and arbitrary synchronized FFs.
      2. This machine should have some practical meaning and be NOT taken from books.
      3. Draw its transition table.
      4. Draw its excitation table.
      5. Draw the schematic.
      6. Analyze the behavior and prove the correctness.
      7. Optimize logic for area and speed.
      8. You may use any logic synthesis technique described so far in this class.
      9. Add the homework to your WWW Page.

   WEDNESDAY, OCTOBER 13, 1999

   MONDAY, OCTOBER 18, 1999

5. Introduction to State Assignment.
6. State Assignment based on rules and hypercubes.
7. State Assignment based on partitions and partition pairs.
8. The multi-line method.

   WEDNESDAY, OCTOBER 20, 1999

9. Description of projects for the class: Functional Decomposition for Machine Learning,

   MONDAY, OCTOBER 25, 1999

10. Description of projects for the class: Machine Learning, Cube Calculus Machine, Linearly-Independent Lattice Diagrams and Self-Repair.
11. New trees and expansions for Reed-Muller Logic.

    WEDNESDAY, OCTOBER 27, 1999

    
    MIDTERM EXAMINATION. Take-home, everybody obtains his own set of problems.
12. Presentation by Nouraddin Alhagi and Seyda Mohsina Afroze about Cube Calculus, Positional Notation and fundamentals of CCM.

    MONDAY, NOVEMBER 1, 1999

13. Presentation by Jacob Boles about Satisfiability/ESOP machine.
14. Presentation by Nouraddin Alhagi on Cellular Automata.

    WEDNESDAY, NOVEMBER 3, 1999

15. Presentation by Decomposition-Machine group. Strategies for decomposition. (Ana, Leonardo, Steven).
16. Presentation by Steve Harwood and Andrew Jackson on Spread Spectrum Transmitter.
    Linear Shift Register Circuit.
    Arithmetics: Multiplier.

    MONDAY, NOVEMBER 8, 1999

17. Presentation by Xiong Wei about convolution-based image processing. Matrix interpretation of Kronecker multiplication.

    WEDNESDAY, NOVEMBER 10, 1999

18. Presentation of Anas Al-Rabadi on Machine Learning for robotics, especially using Constructive Induction.
19. Presentation by Lattice-Self-Repair group. (Dipal Shah and Mr. Merhout).

    MONDAY, NOVEMBER 15, 1999

20. Presentation by Allen Taylor on DNA code cracking.
21. Presentation by Decomposition-Machine group. Variable Partitioning. (Steven).

    WEDNESDAY, NOVEMBER 17, 1999

22. Presentation of Mr. Crown on Machine Learning in Rule-Based systems.
23. Review on Davio expansions, trees and diagrams, multi-valued logic.

    MONDAY, NOVEMBER 22, 1999

24. Post Literals, Generalized Literals and Universal Literals for MV logic.
25. Tree as a starting point to flattened canonical forms, non-canonical expressions, and Decision Diagrams.
26. Generalized Green/Sasao hierarchy for Multi-valued logic.
27. Trees and Diagrams: Kronecker-type, versus pseudo-Kronecker-type, versus Free, versus Lattice Expansions.

    WEDNESDAY, NOVEMBER 24, 1999

28. Genetic Algorithms and Genetic Programming in Logic Synthesis, particularly in Generalized Reed-Muller.
29. FINAL EXAMINATION HAS BEEN ASSIGNED. SEE TO CLASS MAIN PAGE. IT IS THERE.
    All solutions should be in PowerPoint and delivered to me on diskettes.
    
    Everybody has a set of two different problems.
    The exam will have two parts:
    1. TWO Questions related to class material. Problems to solve. About 10 slides each.
    2. Presentations related to your project. As many slides as you feel necessary.

    MONDAY, NOVEMBER 29, 1999

30. Genetic Algorithms and Genetic Programming in Logic Synthesis, particularly in Multi-valued logic.
31. Continuation on generalized Green/Sasao hierarchy for Multi-valued logic.
32. Multi-level networks and rule-based systems.

    WEDNESDAY, DECEMBER 1, 1998.

33. Multi-level networks and rule-based systems.
34. Boolean networks and don't cares.
35. Technology Mapping.

    MONDAY, DECEMBER 6, 1998.

36. Technology Mapping.
37. ...

    WEDNESDAY, DECEMBER 8, 1998.

38. Presentation by Anas Al-Rabadi about Spectral Decision Diagrams.

    SATURDAY, DECEMBER 11, 1999.

39. FINAL EXAMINATION SHOULD BE RETURNED. ABSOLUTE DEADLINE AND THIS TIME I WILL BE FIRM.

    SUNDAY, DECEMBER 12, 1999.

    The last day to return project descriptions. 8pm. in the evening. FALL QUARTER OFICIALLY ENDS.