QUESTIONS TO MIDTERM ONE

SYMMETRY OF BOOLEAN FUNCTIONS.

1. What is a symmetrical Boolean function? Give a precize definition.
2. Explain how to test if a given function, specified as an ARRAY OF CUBES, is symmetrical?
3. How to test a function, specified as an array of cubes, for all possible partial symmetries of subsets of variables?
4. How to generalize the concept of partial symmetry of variables?
5. Given is the set of ALL symmetric functions specified by four indices: F1 = S^{i11,i12,i13,i14}(a,b,c,d,e,f,g,h), F2 = S^{i21,i22,i23,i24}(a,b,c,d,e,f,g,h),
   ...
   Fz = S^{z1,z2,z3,z4}(a,b,c,d,e,f,g,h). Calculate, how many such functions exist for arguments {a,b,c,d,e,f,g,h}. (how much is z?).
   Create a regular structure in which EVERY function Fi would be programmable. The structure must be a generalization of PLAs and multiplexer-based symmetric structures from the class. Explain how to program this structure. Give an example.
6. Give all applications of this structure that you may think of.

PATTERN MATCHING SEQUENCES.

1. The pattern is composed of symbols: A, B, C, D.
   The pattern has an arbitrary number of repetitions of any symbols, in any order. Any symbol can be repeated arbitrary number of times in the sequence, and the number of sequences of symbols is unlimited.
   For instance: AAAABBBBBBAAAAAACCADDAAA
   Set of such patterns is denoted by SPAT.
   For instance, SPAT_1 = {AABB, ACCD, ABCD}
   
   1. Create a methodology of designing automatically iterative combinational circuits: pattern recognizers for any sets SPAT_i. Use one-dimensional array of identical blocks, realized by PLAs. Draw the schematics.
   2. Create a methodology of designing automatically SEQUENTIAL pattern recognizers for any sets SPAT_i. Use a PLA for logic, and a register from D flip-flops. How much of the methodology from point a) you can re-use without any modifications?

VHDL PROJECTS.

1. What did you learn by doing VHDL homeworks and projects? Write very specifically.
2. What else would you like to learn in projects?
3. Do you have any "dream project ideas", like designing a general purpose computer? Describe them in more detail, at a behavioral, or RTL levels. (but not in VHDL).

   DESIGN OF A GENERAL-PURPOSE PARALLE AND SERIAL COMPUTER.

   1. Given is a data path composed of 8 registers, A,B,C,D,E,F,G,H. Assume registers 16 bits each.
      Any of the following instructions must be executed in the data path of your computer:
      R_i R_j --> R_k
      where R_i, R_j, and R_k are any of 8 registers, or any constant: 0, 1, -1, 2.
      For instance: A + B --> A, A - C -> D, A AND B -> C
      is any of the following:
      a) any Boolean function of two variables, extended for words, like A EXOR B -> D
      b) arithmetic addition, A + B -> E.
      c) arithmetic subtraction, C - D -> H, - D -> D.
      One of registers, say A, should be a STATE REGISTER (program counter). Another of the registers, say B, is the Memory Buffer register of a RAM memory, controlled with READ, WRITE and ADDRESS signals. Yet another register, say C, is the Memory Address register.
      
      1. Design the control word for this computer, so that it will encode all possible instructions specified as above. Draw the RTL description of the Data Path. Show how the control word is decoded to control transfers between registers.
      2. Is this a general purpose computer? If yes, prove that your computer is a general-purpose computer, by demonstrating that you can emulate a Turing Machine, a Post Machine, or any other known general-purpose computer on your computer.
         If your computer (controller plus data path) it not yet a general-purpose one, add as little hardware as possible to make it a general-purpose computer. Prove that it is a general computer.
         
      3. From a conceptual version of the computer, design two versions of your computer: version one with serial execution of all operations. version two with parallel execution of operations. Design both the controller, and the data path, but not at the circuit level. Designing a state machine and/or RTL description with explanation is OK.
         The computer should have no input/output. Memory corresponds to the tape of Turing Machine. Do not worry how to fill and read the memory.

   TIMING OPTIMIZATION FOR A GENERAL-PURPOSE COMPUTER.

   
   Solve problem 4, but only for the parallel version. In this variant, however, design the computer on the circuit level, and optimize timing. (of course, you do not need to repeat the cell design for all 16 bits, etc. Just explain me clearly what you do). Make it a pipelined computer, as fast as possible by having as little logic levels between registers as possible. Assume that you design everything from D flip-flops connected to a single clock, and two-input gates corresponding to arbitrary logic functions of 2 inputs. Each gate has a delay of TAU. Do not assume any other delays. The goal of using pipelining in your design is to optimize it for speed. Evaluate times for all your operations, use the units of TAU.

SIMILARITY OF BASIC COMBINATORIAL PROBLEMS OF BOOLEAN ALGEBRA

1. Petrick Function.
2. Satisfiability POS formula (Product of Sums of Literals).
3. Minimal Covering Problem.
4. Satisfiability Problem.
5. Tautology Problem.