EE 574/ EE 674: SYSTEM LEVEL DESIGN AUTOMATION, HIGH LEVEL SYNTHESIS, AND SOFTWARE-HARDWARE CODESIGN

Marek A. Perkowski

Department of Electrical Enginering.

Catalog Description of the proposed Course sequence.


Behavioral, functional, structural and register-transfer descriptions.
Algorithmic State Machines. Fundamentals of Hardware Description Languages.
Simulation.  Levels of system simulation.
Current extensions of language VHDL and expandable languages.
Specification of controllers and data path architectures.
Microprogramming and systematic design of control units.
Hardware scheduling and allocation.
Automatic System Verification.
Software-hardware codesign.
VHDL for systems from Field Programmable Gate Arrays.
Emulators and Xputers.
Examples and applications of complete systems.
Several computer-based software mini-projects.  Discussion of projects.

TOPICS BY HOUR:

 1. Comprehensive design automation systems (3 hours).
 2. Regular expressions, Petri Nets and other hardware description methods (3 hours).
 3. Problems of system and high-level synthesis and verification (4 hours).
 4. Register-transfer notation and design (3 hours).
 5. Approaches to Hardware Verification (5 hours).
 6. Methods and languages to specify hardware, system hardware-sofware codesign (3 hours).
 7. Data path design (4 hours).
 8. Scheduling and allocation (3 hours).
 9. Design methods for systolic and pipelined computers (2 hours).
10. FPGA technologies, FPGA-based prototyping and emulation (5 hours).
11. Cellular and dynamic architectures (3 hours).
12. Microprograming and microprogram optimization (2 hours).
  • PREREQUISITE: graduate standing in EE.
  • TEXTBOOKS:

    GOALS:

    LAB PROJECTS

    COMPUTER USAGE:

    SUN SPARC Stations are used to run Mentor, Cypress, Orcad, DEC, Analogy Inc., and various public-domain and university design tools and simulators.

    ESTIMATED CONTENT:

    ADDITIONAL INFORMATION:

    The grading policy is as follows:

    MORE DETAILED SPECIFICATION OF TOPICS:


    Some of the topics change every year, depending on selected projects and students' interests.

    TUESDAY, MARCH 30

  • What is this class about.
    The goal of the class is to learn how to verify your design
    and next how to use CAD tools for automatic design free from errors.
    Verification will be done in Prolog.
    Next the design will be transformed to VHDL, schematic capture or Summit tools.
    Next the design will be synthesized using Xilinx or Altera tools. (option, for some projects only).
    The groups of students will be created.
  • Introduction to Automatic Theorem Proving and Prolog language.
  • Predicate Calculus versus Boolean Logic, quantifiers (Chapter 12 from my book).

    THURSDAY, APRIL 1

  • Automatic Theorem Proving.
    Clauses, Horn Clauses, Substitution, Resolution, Unification.
  • Examples of reasoning: forward, backward.
  • Prolog language.
    Simple question answering, logic puzzles, family databases.

    TUESDAY, APRIL 6

  • Presentation and discussion of projects.
  • Brief presentation of the DEC PERLE board and the discussion of mapping to it.
  • List processing and automatic theorem proving in Prolog.

    THURSDAY, APRIL 8

  • Examples of Test Generation and Verification in Prolog.
  • Formal Synthesis correct from specification: Regular Expressions in Prolog.
  • Fundamentals of verification.
  • Verification of a multiplier.

    TUESDAY, APRIL 13

  • Various approaches to formal verification.
  • Sequent calculus: Petri Nets, Flowcharts, natural language described machines.
  • Sequent calculus: Mealy and Moore Machines, Data Path circuits.

    THURSDAY, APRIL 15

  • Student Presentations.
  • Designs correct from specifications. Transformational design methods.

    TUESDAY, APRIL 20

  • CAD tools for logic specification, simulation and synthesis.
  • Introduction to EPLDs and FPGAs.
  • Xilinx chips.
  • Altera chips.

    THURSDAY, APRIL 22

  • CAD tools for logic verification.
  • FPGA computing.

    TUESDAY, APRIL 27

  • Formal verification algorithms based on theorem proving in higher order logic.

    THURSDAY, APRIL 29

  • Formal verification in HOL, introduction.
  • Principle of perfect induction.

    TUESDAY, MAY 4

  • Lecture: Formal verification in HOL, verifying Comparator, Counter, Shifter and Serial
  • to Parallel converter.

    THURSDAY, MAY 6

  • Lecture: formal verification based on automatic theorem proving.
  • HOL: Verifying microprograms. Verifying multiplier.

    TUESDAY, MAY 11

  • Lecture: formal verification based on automatic theorem proving.
  • Using FOL for adder and microprograms.

    THURSDAY, MAY 13

  • Lecture: formal verification based on automatic theorem proving.
  • Using Boyer-Moore to prove correctness of circuit generators.

    TUESDAY, MAY 18

  • Examples of formal verification on simple examples.

    THURSDAY, MAY 20

  • I am absent, attending ISMVL'99.
  • Please meet in class and discuss your projects.
  • Student Presentations (videotaped?).

    TUESDAY, MAY 25.

  • Using Boyer-Moore to proove correctness of circuit generators.
  • Using Relational System.
  • Examples of formal verification performed by students on simple examples.

    THURSDAY, MAY 27

  • Repetition and projects discussions. New approaches and systems for formal verification/design.
  • Student Presentations (videotaped?).

    MONDAY, JUNE 1.

  • Lecture: formal verification based on functions.
  • Lecture: formal verification based on state machines.
  • Presentation and discussion of projects.

    THURSDAY, JUNE 3.

  • Classical and Modern Decision Diagrams.
  • Model Checking.

    TUESDAY, JUNE 8.

  • Model Checking (cont).

    THURSDAY, JUNE 10.

  • Final presentations and discussions of class projects.

    SUNDAY, JUNE 13.

    Last day of accepting class reports.

    http://www.ee.pdx.edu/~mperkows/ADL/ADL_EXAMPLES