TESTING AND DESIGN FOR TEST, FALL 2001

INSTRUCTOR: Marek Perkowski, Professor of Electrical and Computer Engineering

INSTRUCTOR'S OFFICE: room FAB 160-05 , PSU Campus, Fourth Avenue Building.

The class will be taught at PSU Campus, room CECS 54 (formerly SA 54, SEAS ANNEX).

THIS NEW CLASS IS AVAILABLE TO UNDERGRADUATE STUDENTS AS WELL.

CLASS LOCATION: ROOM CECS 54. THE SAME BUILDING AS THE OLD BOOKSTORE. TUESDAYS AND THURSDAYS, 6:40 P.M. Starts on Tuesday, September 25th.


  • CLASS TITLE: Test and Design for Testability.

  • TEXTBOOK: Abramovici, Breuer, Friedman: ``Digital Systems Testing and Testable Design''. IEEE Press, Revised Printing, 1995. Can be ordered directly on the Internet. This is a "Bible" and includes nearly everything we discuss in class, and much more.
    ALL NECESSARY CLASS MATERIAL IS IN THE SLIDES AVAILABLE ON INTERNET.

  • ADDITIONAL TEXTBOOKS AND MATERIALS:
  • Christian Landrault `` Test and Design for Test of Integrated Logic Circuits,''
    - translated by M. Perkowski. Available from professor or from Smart Copy.
    - also available on WWW Page for registered students. Password will be given in class.
    - Power Point slides will be also available for registered students. Password will be given in class. This book is very close to my interests and includes much material. Unfortunately, it does not go to sufficient depth. Used in France.
  • Alfred L. Crouch, ``Design for Test. For Digital IC's and Embedded Core Systems''. Prentice Hall, corrected edition, March 2000. This book is recommended by several IC and DFT companies in USA. Very practical and modern, but not comprehensive.
  • Hideo Fujiwara,
    ``Logic Testing and Design for Testability,'' The MIT Press, available from the Professor. This is a short book with good explanation of principles.

    M. Perkowski ``Notes and Papers on Test.''
    - Available from professor, for projects only.
    All books are available from Powell's Bookstore.


  • PREREQUISITIES:
    This is an introductory class in testing.
    Only sophomore-level knowledge of combinational logic and state machine design is assumed.


  • WHAT YOU WILL LEARN:
    1. This class will give you a complete understanding of basic issues in testing and design for test, DFT.
    2. For instance, you will be able to create a minimum set of tests to test any combinational or sequential circuit and to localize and diagnose faults in this circuit.
    3. It will give you also an in-depth understanding of several modern issues and work in progress.
    4. You will practically use modern test and "Design for Test" (DFT) software tools for your own logic circuits.
    5. Quite possibly, you will do a publishable-quality research work and be able to publish a collaborative paper in top journals such as IEEE Transactions on Computers, IEEE Transactions on CAD, or VLSI Design Journal (for volunteers and Ph.D. level students only).
    6. You will learn how to use Mentor VHDL-test tools, PowerPoint and you will have to create a web page.


  • GRADING POLICY:

    There will be four projects, a written midterm, and a written final exam.

    Project 1: 10%
    Test generation using various representations. Preset and adaptive fault localization .
    Students will have to create their own Web Pages for the class. They have also to create Power Point slides for all their reports, put them to their webpages, and use them in their class presentations (lectures).
    This project will be assigned at the first meeting of the class.
    It will be recommended to use ASTER software, available for free for all class students.
    This program is available on the WWW Page of Alan Mishchenko.

    Project 2: 15%
    In your web page, create a link with test-related issue of your choice . The link should include your Power Point slides and links to WWW Pages of other authors on this topic.
    This project will involve self-study and may conclude in journal/conference publication.
    The choice should be done based on class discussions and PDF-formatted papers from the class WWW Page.
    All your pages will be linked to my WWW Test page.

    Project 3: 10%
    Modern integrated test and validation systems - theory - presentation.
    please make plans for 30 minutes of presentation using your PPT transparencies. This should be the same topic as presented in your webpage.

    Project 4: 30%
    Individual test and validation related research project of your choice.
    The list of projects will be assigned in the second week of classes.
    You can also propose your own project. This year the projects will be related to testing of reversible logic circuits.

    Midterm Exam: 15%
    take-home exam, open book, comprehensive, study of test ideas.

    Final Exam: 20%
    take-home exam. Open book, comprehensive, study of test ideas.


    The course presents the fundamental theory for
    test of electronic circuits with specific emphasis on the design of highly
    testable digital integrated circuits.


    The aim is to give an introduction to
    the testing problem for integrated circuits,
    enabling the participants to design integrated circuits of high test quality.

    This class can be of use to both circuit designers and CAD/EDA tool designers.

  • TOPICS TO BE DISCUSSED WILL INCLUDE:

    1. Fault Modeling.
    2. Testing Problems and Schemes.
    3. Test Generation.
    4. Boolean Difference.
    5. The D-Algorithm.
    6. The PODEM Algorithm.
    7. Test Generation for Sequential Circuits.
    8. Fault Simulation Methodology.
    9. Parallel Fault Simulation.
    10. Deductive Fault Simulation.
    11. Concurrent Fault Simulation.
    12. Hardware Simulators.
    13. The Complexity of Testing.
    14. Introduction to Design for Testability.
    15. Minimization of Testing Cost.
    16. Combinational Logic Versus Sequential Logic.
    17. Ad Hoc Design and Structured Design.
    18. Design to Minimize the Cost of Test Application.
    19. Minimally Testable Design.
    20. Design to Minimize the Cost of Test Generation.
    21. Partitioning and Exhaustive Testing.
    22. Syndrome-Testable Design.
    23. Highly Testable Reed-Muller Canonical Forms. (and PSU's published contributions).
    24. Programmable Logic Arrays.
    25. Scan Design for Sequential Logic Circuits.
    26. State-Shiftable Machines.
    27. Incomplete Scan Design and Enhanced Scan Design.
    28. Design for Built-in Self-Testing.
    29. Signature Analysis.
    30. Built-In Logic Block Observer.
    31. Self-Test with Scan Design.
    32. Universal test for fault localization in regular structures (with our published contributions).
    33. Self-Repairable regular structures (with our published contributions).
    34. Robots for testing.

    DEAR UNDERGRADUATE STUDENT

    IF YOU ARE INTERESTED IN:
    1. DESIGNING HIGHLY TESTABLE DIGITAL CIRCUITS,
    2. LEARNING PRACTICAL METHODS USED IN INDUSTRY SUCH AS BIST,
    3. SELF-REPAIRABLE FPGAS,
    4. DESIGN FOR TEST OF CIRCUITS WITH EXTREMELY SHORT TESTS, OR
    5. PROGRAMMING A ROBOTIC ARM TO HANDLE AUTOMATIC TEST AND FAULT LOCATION OF ELECTRONIC BOARDS,


    THIS CLASS IS FOR YOU.
  • Contact me if you have any questions.



    • THESE, AMONG OTHERS, COULD BE YOUR PROJECTS IN YEAR 2001:.



    This is our robot setup for testing boards. The board is taken by the robotic arm from the conveyor belt, tested electrically using student-developed software for test and fault localization, and repaired automatically. The Professor Head (a robot) explains the experiments to the students by voice.




    Graphics Interface to Aster program developed by Alan Mishchenko. Your task will be to link your software to this program to visualize your testing methodology and algorithms.