This class has number ECE 510DT for undergraduates, ECE 510 for M.S. students and ECE 610 for Ph.D. students.
The difference is that more advanced students work on more difficult projects.

Marek Perkowski, Professor of Electrical and Computer Engineering

CLASS SCHEDULE

This schedule may be changed as I will learn more about your project interests, programming strengths and backgrounds.

TUESDAY, SEPTEMBER 28, 1999

Introductory Lecture. Books, WWW Pages, Information. Class schedule. Grading Policies. This class will introduce the concept of design for test of EXOR-based circuits.
This will be one of the topics of class projects for this quarter.
Stuck-at-0,
Stuck-at-1,
Bridging faults,
(Positive Polarity) Reed-Muller Forms,
Fixed Polarity Reed-Muller Forms,
Generalized Reed-Muller Forms,
Universal Tests, Test generation methods for RM, FPRM and GRM.
Genetic Algorithms
Using Genetic Algorithms for GRM and Test generation.
Open Problems and class projects.

PROJECT "THE TESTING ROBOT".
(individual work of creative type, publishable, thesis material).
this needs to be professionally edited as explained below.
AUTHORS: Anas (manager) and Justin.
TITLE: Use of Rhino robot for test, diagnosis and self-repair of PCBs. TO: Anas and Justin, I need your short document with project description at the first meeting of the second week. TO: ALL OTHER STUDENTS I need your short document with YOUR project descriptions.
You can have your choice or I will propose.
Let us talk about it.

THURSDAY, 30 SEPTEMBER, 1999.


Basic concepts: fault and test.
The concept of stuck-at faults.
Representations of Boolean Functions.
- Sum of Products (SOP), Disjoint Sum of Products (DSOP),
- Exclusive Sum of Products (ESOP),
- (Positive Polarity) Reed-Muller Form (PPRM),
- Fixed-Polarity Reed-Muller Form (FPRM),
- Generalized Reed-Muller Form (FPRM),
Examples of test generation.
Boolean Difference and its use for test generation.
Using Boolean Difference with various above representations of functions.

TUESDAY, OCTOBER 5, 1999.


Properties of Boolean Difference.
Use of Boolean Difference for test generation of internal signals.
Test table, minimization techniques for test table.
- dominations, equivalence of rows and columns,
- Petrick Method, Branching methods. Storage efficiency.
Fault location, preset and adaptive algorithms.
Creation of Diagnostic Trees and Diagrams.

THURSDAY, OCTOBER 7, 1999.


Positional Notation of Cube Calculus.
Realization of efficient programs for cofactors and Boolean Difference.
Binary Decision Diagrams.
Functional Decision Diagrams.
Ordered Kronecker Decision Diagrams.

ASSIGNMENT OF PROJECT NUMBER THREE (conference paper reading and class presentation - individual project).
Every student reads a current paper from Test Conference and presents it in class.
This project should be either delivered as a report (see below) or as a WWW HTML page.

TUESDAY, OCTOBER 12, 1999.


Path Propagation.
Multiple Fault Models, Testing PLAs and regular structures.
Test and Test Economics.

THURSDAY, OCTOBER 14, 1999.


Test and Test Economics (cont).
Testability Measures.
Test generation algorithms and programs.
  • Test generation for AND/EXOR circuits.
    Modifications of EXOR logic circuits for better observability and controllability.

    TUESDAY, OCTOBER 19, 1999.


    Test generation algorithms and programs.
  • Explanation of project on DFT.
    Critical analysis of Sasao's paper. click here to get Sasao's paper ONLY FOR IEEE MEMBERS.
  • Self-test and Self-repair. Choices of the best architecture.
    Discussion of the document ``Design of Self-Repairable Electronically Programmable
    Logic Devices''.
  • New commercial test tools from Synopsys.

    THURSDAY, OCTOBER 21, 1999.


    Explanation of projects: Design for test: Reddy paper about PPRM, Sasao's GRM, our ESOP.
    What needs to be done in this matter.

    TUESDAY, OCTOBER 26, 1999.

  • testability issues and video about test technology related to design and manufacturability in industry. We meet in PCAT building, next we go to FAB for Anas/Justin presentation.
    PROJECT "TESTING ROBOT" STUDENT PRESENTATION.
    - Each student presents using his transparencies or PPT.
    - Each student presents his lecture in class - plan to deliver 30 minutes talk.
    - You can purchase folies from the secretary in ECE office and use standard Xcopy machine at PSU for your transparencies. You can also draw transparencies by hand.

    THURSDAY, OCTOBER 28, 1999.

  • Discussion about testability of EXOR circuits.
  • Tree, versus DAG, versus cascade in output.
  • Simple versus multiple faults.
  • Circuit's Adaptation for more controllability: how many additional inputs?
  • Circuit's Adaptation for more observability: how many additional outputs?
  • Modified vs non-modified circuits, universal vs non-universal test sequences.
  • Test complexity for various approaches and its importance.

    TUESDAY, NOVEMBER 2, 1999.

  • Nagesh and Ojha: Presentation of "VHDL/BIST INSERTION PROJECT".
  • Scan Test Techniques.
  • Research of Reddy, Saluja, Pradhan, Sasao and Kalay on testable canonical AND/EXOR forms.

    THURSDAY, NOVEMBER 4, 1999.

  • Factorized ESOP Circuits for high testability.
  • New ideas in EXOR testability, trees, lattices.

    TUESDAY, NOVEMBER 9, 1999.

  • Galois Field Circuits for high testability.
  • Boolean Ring Circuits for high testability.

    THURSDAY, NOVEMBER 11, 1999.

  • NO CLASS, Veterans Day.

    TUESDAY, NOVEMBER 16, 1999.

  • Alan Mishchenko's presentation on universal simulator, fault simulator and fault locater using multiple-valued BDDs. The essence of fault simulation using implicit methods.

    THURSDAY, NOVEMBER 18, 1999.

  • Sequential test: main ideas and approaches.
  • Experiments with Finite State Machines: Homing, diagnosis, synchronizing sequence, experimentation. Functional tests for sequential circuits.

    TUESDAY, NOVEMBER 23, 1999.

  • Sequential test. Uses of Distinguishing sequences. Boundary Scan. LFSR. MISR.

    THURSDAY, NOVEMBER 25, 1999.

  • NO CLASS, THANKSGIVING.

    TUESDAY, NOVEMBER 30, 1999.

  • More advanced material on boundary scan, BIST and BILBO. I.
  • Description of Mentor's tools for test and BIST tools.

    THURSDAY, DECEMBER 2, 1999.

  • D algorithm, PODEM, FAN.

    TUESDAY, DECEMBER 7, 1999.

  • Spectral methods. Delay faults.

    THURSDAY, DECEMBER 9, 1999.

  • Visit and lecture of a person from Mentor Graphics test division.
    This is the last day of the class.

    SATURDAY, DECEMBER 11, 1999.

    LAST DAY TO RETURN ALL REMAINING PROJECTS. RETURN TO MY ROOM BEFORE: 8 p.m. FALL QUARTER OFICIALLY ENDS.

    MONDAY, DECEMBER 13, 1999.

    ALL GRADES MUST BE DELIVERED BY ME AT TO THE E.E. OFFICE BEFORE 11:45 A.M. THE GRADES WILL BE BASED ON YOUR EARLY HOMEWORKS AND PREDOMINANTLY ON THE PROJECTS.


  • PROJECT REPORT EXPLANATIONS:


      Reports of projects (other than project two) must be written in Latex or other word processor, preverably Latex,
      with the idea of your project, explanation of your design options
      and variants, design of control unit and data path, and description of all
      smart trick or design techniques that you used.

    • READING PROJECT (PROJECT NUMBER FOUR) REPORT EXPLANATIONS:
      FOR HTML Project:
      I need HTML WWW Page with your report send to me by email.
      You can edit HTML with vi, Interleaf, Word, or any editor.
      Interleaf and Word generate it automatically.
      You can use Interleaf or Slidex (Latex2e-based) to generate slides.
      Postscript can be converted to HTML using Webify.
      Postscript can be converted to gif using ps2gif.
      Latex can be converted to HTML using Latex2Html.
      All your reports will be incorporated to my WWW Page.
      You may want to use them in your pages as well.
      I PREFER WORD TEXT AND POWER POINT presentation, you can easily convert them to WWW Page.

    • VHDL PROJECT REPORT EXPLANATIONS:
      - Full VHDL code with comments,
      - explanation of all names and full annotation at the beginning of each part.
      - Full results of simulation. Diagrams with comments. I will not accept diagrams only without your comments on them.
      - You have to send me these reports, VHDL files, and result files by mail as tar files or attachments.