INTRODUCTION TO STUCK-AT FAULT MODEL AND TESTS.

1. READ chapter 1 in Landrault.
2. READ first part of testability chapter in Hurst.
3. READ introduction ot Fujiwara.
4. READ Kohavi chapter 8, sections 8.1 to 8.5 about test.
5. Basic concepts: fault and test.
6. The concept of stuck-at faults. Stuck-at-0, Stuck-at-1.
7. Representations of Boolean Functions.
   - Sum of Products (SOP), Disjoint Sum of Products (DSOP),
   - Exclusive Sum of Products (ESOP),
   - (Positive Polarity) Reed-Muller Form (PPRM),
   - Fixed-Polarity Reed-Muller Form (FPRM),
   - Generalized Reed-Muller Form (FPRM),
8. Examples of test generation.
9. Boolean Difference and its use for test generation.
10. Using Boolean Difference with various above representations of functions.
11. Properties of Boolean Difference.
    
12. Bridging faults,
    
13. (Positive Polarity) Reed-Muller Forms,
    
14. Fixed Polarity Reed-Muller Forms,
    
15. Generalized Reed-Muller Forms,
    
16. Universal Tests, Test generation methods for RM, FPRM and GRM.
    
17. Genetic Algorithms
    
18. Using Genetic Algorithms for GRM and Test generation.
    
19. Open Problems and class projects.
    

MORE ADVANCED TOPICS RELATED TO STUCK-AT FAULT MODEL AND TESTS.

1. Design for Test of Combinational Circuits using high percent of EXOR gates.
   Specifically:
   Factorized AND/EXOR structures.
   SOP/EXOR structures.
   Develop efficient test generation methods for above structures.
2. Use of Boolean Difference for test generation of internal signals.
3. Test table, minimization techniques for test table.
   - dominations, equivalence of rows and columns,
   - Petrick Method, Branching methods. Storage efficiency.
4. Fault location, preset and adaptive algorithms.
5. Creation of Diagnostic Trees and Diagrams.
6. Positional Notation of Cube Calculus.
7. Realization of efficient programs for cofactors and Boolean Difference.
8. Binary Decision Diagrams and applications.
9. Functional Decision Diagrams.
10. Ordered Kronecker Decision Diagrams.
11. Test generation for AND/EXOR circuits.
12. Modifications of EXOR logic circuits for better observability and controllability.
    Critical analysis of Sasao's paper. click here to get Sasao's paper
13. Discussion about testability of EXOR circuits.
14. Tree, versus DAG, versus cascade in output.
15. Simple versus multiple faults.
16. Circuit's Adaptation for more controllability: how many additional inputs?
17. Circuit's Adaptation for more observability: how many additional outputs?
18. Modified vs non-modified circuits, universal vs non-universal test sequences.
19. Test complexity for various approaches and its importance.
    
20. Test Generation (PS 786K)
    (PDF 208K)
    
    

PATH PROPAGATION METHODS. MULTIPLE FAULTS.

1. Path Propagation.
2. Multiple Fault Models, Testing PLAs and regular structures.
3. Test and Test Economics.

TESTABILITY OF TWO-LEVEL CIRCUITS.

1. Testability of Two-Level Circuits (PS 568K)
   (PDF 144K)
   
   

TESTABILITY OF MULTILEVEL CIRCUITS.

1. Testability of Multilevel Circuits (PS 590K)
   (PDF 168K)
   

FAULT MODELS.

1. Chapter 2 in Landrault.

TESTABILITY MEASURES.

1. Chapter 3 in Landrault.
2. SCOAP examples. Testability Measures.
3. Advanced Testability Programs.

PATH PROPAGATION METHODS. MULTIPLE FAULTS.

1. Chapter 4 in Landrault.
2. Test and Test Economics (cont).
3. Test generation algorithms and programs.

FAULT SIMULATION.

1. Chapter 5 in Landrault.
2. Simple Pascal simulator.
3. Adaptations for fault simulation.
4. Multiple-valued logics for simulation.

SELF-TEST AND SELF-REPAIR.

1. Self-test and Self-repair. Choices of the best architecture.
2. Discussion of the document ``Design of Self-Repairable Electronically Programmable Logic Devices''.
3. Literature reading about self-repair of memories, FPGAs and EPLDs. Genetic Hardware.
4. Look to commercial test tools.

VHDL AND MUTATION TESTING.

1. Project about test generation from VHDL using mutation testing.
2. Paper: Ghassan Al Hayek and Chantal Robach, ``From Specification Validation
   to Hardware Testing: A Unified Approach, ITC, 1996, pp. 885 - 893.
3. testability issues and video about test technology related to design and manufacturability in industry. Read this

TESTING SEQUENTIAL CIRCUITS.

1. Kohavi chapter 13 about experiments with automata.
2. Experiments with Finite State Machines: Homing, diagnosis, synchronizing sequence, experimentation.
3. Functional tests for sequential circuits. Difficulties.

SCAN TECHNIQUES.

1. Chapters 6 and 7 from Ladrault.
2. Scan Test Techniques.
3. Approaches of IBM, Philips, NEC, Stanford.
4. Boundary Scan.
5. Built-In Self Test (BIST).
   read about Logic Vision, the pioneer in Bist. look to products and tutorials.
   BIST for mixed and analog circuits.
   
   
   Short Description of tools from Mentor.
   DFT from Mentor.
   LBIST Architect from Mentor.
   MBISTA from Mentor.
   HOT TOOLS
   
6. Linear Automata and signatures.

USING LBIST ARCHITECT FROM MENTOR.

1. Mentor WWW Pages and Manuals.
2. Design a small Glushkov Machine from Control Unit and Data Path.
   Examples include:
   - Fibonacci sequence generator.
   - Greatest Common Divider.
   - Code recognition.
   - Waveform generation.
   - Programmable industrial controllers of processes.
   See also my VHDL class.
3. Create a VHDL for it.
4. Insert automatically BIST and compare the two solutions.
5. Write a report and create a Web Page reporting your work.
6. HERE, there is a good page example of another VHDL project. Pavel's Kashubin and friend project.

ADVANCED SELF-TEST TECHNIQUES AND RELIABLE CIRCUIS.

1. Chapter 8 from Ladrault.
3. Kohavi chapter, the following sections:
   Failure-Tolerant Design
   Quadded Logic
   
   

TAUTOLOGY AND VERIFICATION.

1. Two-Level Tautology and Verification (PS 661K) (PDF 86K)
   

VERIFICATION OF SEQUENTIAL CIRCUITS.

1. Sequential Circuit Verification (PS 709K)
   (PDF 176K)
   
   

ADVANCED METHODS FOR TESTING OF SEQUENTIAL CIRCUITS.

1. Sequential Circuit Testing (PS 144K)
   (PDF 112K)
   
   

DESIGN VERIFICATION.

1. Design Verification (PS 917K)
   (PDF 120K)