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BUILT-IN SELF TEST
Semiconductor makers eye built-in self-test to handle complex circuits By Robert Ristelhueber (Illustration by David Chen) There's no doubt that many semiconductor makers today are capable of producing a system on a chip. But can they also reliably and affordably test it? Concerns about that are sparking interest in built-in self-test (BIST), an approach in which a chip largely performs the test functions itself. The problem of test has grown as integrated circuits (ICs) have become faster and more complex. High-speed testers cost millions of dollars, and physical access to internal circuitry becomes tougher as the number of I/O pins fails to grow as quickly as the logic content. The advent of system-on-a-chip designs has compounded the difficulty. These devices may contain embedded memories and intellectual property (IP) acquired from a variety of vendors, who often provide sketchy details about the designs of these cores, complicating the test procedure. Several electronic design automation (EDA) companies are pushing BIST as a solution. With this technique, the tester functionality is embedded as a controller on the IC during the chip's design phase. A low-cost external tester signals this controller to generate random test patterns, and then later reads the results.
Using an ASIC (application-specific integrated circuit) or FPGA (field programmable gate array), the technique can be extended to board- and system-level testing, allowing continual monitoring. Although BIST has been largely confined to mission-critical and fault-tolerant products, the advent of system-on-silicon may change that. BIST is the latest of the techniques called design-for-test (DFT), which also includes the scan technologies. They are, in part, a response to the cost of automatic test equipment, an industry that's grown to between $5 billion and $6 billion a year. "DFT offers a customer an opportunity to reduce the size of that expense," says Mark Olen, product line manager at Mentor GraphicsCorp., Wilsonville, OR. By using a full complement of DFT tools, a customer can buy a 4-pin tester for $50,000, rather than an advanced tester costing a million dollars or more, he asserts. "The holy grail of DFT is to guarantee high quality and reliability while reducing test cost, while making it pretty painless for designers," Olen says. Mentor is sinking considerable research and development spending to achieve that goal, particularly in the BIST area, he says. Some observers contend that BIST is becoming critical to solving the test conundrum. "People have just caught on that this is becoming a major problem," says Gary Smith, analyst with Dataquest in San Jose. "The big box testers are just getting too damn expensive, and you can't use a component tester to solve a system test problem. Most of the test structure will have to be embedded in the design." A number of users agree. "When you have a very large complex chip, you need to develop methods to reduce the cost from the perspective of test time," says Karen Parker, director of product marketing for National Semiconductor Corp.'s LAN Division, Santa Clara. "One method you can use is BIST, so that circuits are virtually testing themselves in parallel." National uses BIST along with mixed-signal testers, which she says are still needed to test analog signals coming out of chips like communications transceivers. Hughes Aircraft has been using BIST techniques since 1987, says Bill Farwell, senior principal engineer of the Electronics Division in El Segundo, CA. "We're building highly reliable fault-tolerant systems that go into aircraft. Even during missions, we have to continuously verify that each part is working perfectly, and we obviously couldn't take testers along." Hughes previously implemented BIST manually, but now uses commercial tools to perform the same tasks. "All else being equal, BIST still gives a better quality level than traditional scan methods, at about the same cost," Farwell says. Still, the need for complex test equipment hasn't vanished because "the vast majority of designs from our ASIC suppliers don't use BIST." Farwell adds that he would like to have more automated BIST tools for board-level and system-level test. Raytheon TI Systems, Plano, TX, has used memory BIST supplied by Mentor Graphics for several ASICs used for data processing. "It's worked out just great because we got at-speed testing," says Greg Young, a group technician. "Scan-based testing wouldn't operate at the same speed, so timing-related faults are not going to show up."
One of the leading proponents and vendors of BIST is LogicVision Inc., San Jose. "With clock speed pushing to 200 megahertz and beyond, it's very difficult for external testers to achieve true at-speed testing," contends Bob Smith, vice president of marketing and business development. "Most designers are forced to accept testing at lower-than-clock speeds," allowing some faulty parts to slip through, he says. Attempts to combat this through methods such as combining scan with automatic test pattern generation (ATPG) have been only partially successful, Smith claims. "We are uncovering faults you wouldn't find using ATPG." The cost of automatic test equipment is also shooting up as chips become more difficult to test, a trend that will only accelerate as designs move to .18 micron and smaller linewidths, Smith says. The 1,000 to 3,000 gates needed to create the on-chip controller used by BIST is considered a small overhead in an era when hundreds of thousands of gates are being crammed into a single chip, Smith says. He contends that dynamic random access memories (DRAMs) will also eventually use BIST, probably at the 256 megabit level, because of bandwidth issues. By using BIST, customers "won't need to rely on multimillion dollar testers for mass manufacturing," Smith says. He contends that users can leverage BIST for maintenance, repair and diagnosis of systems after they enter the field. "The same test can be reused at any point during the lifetime of the chip, board or system." LogicVision charges a license fee of $45,000 per design for an unlimited production run, which gives the customer both logic and memory BIST as well as boundary scan and test access port. The license fee drops depending on the number of designs implemented. Mentor charges $55,000 for its memory BIST tool and $75,000 for its logic BIST tool, but customers can use them for multiple designs, the firm says. Memory BIST has been adopted more quickly than logic BIST, Mentor's Olen says, because "with people embedding megabits of memory in a system-on-a-chip, the need is huge." He predicts that logic BIST will eventually take off, driven by the move toward IP. Cadence Design Systems has integrated test into its design services strategy, licensing DFT tools from LogicVision, Viewlogic/Sunrise and other vendors, says Chit Mallipeddi, vice president of design services, San Jose. "Customers were telling us, 'If you just come back with another tool, it's not going to help us. What we need is someone to help us on test methodology.' " The density, speed and low power characteristics of deep submicron make design-for-test particularly important, he says. Off the wagon Not all EDA vendors have jumped on the BIST bandwagon. Viewlogic Systems Inc., Fremont, CA, has focused on scan technology and ATPG, which is "a more flexible approach," according to Mark Milligan, vice president for the company's Sunrise business unit, which handles design-for-test products. "Logic BIST has its place and is growing, but has been confined to narrow niches like large phone switching equipment and fault-tolerant computers, big systems with a functional requirement to test themselves in the field," Milligan notes. He says it's a fallacy that by using logic BIST, engineers don't need to have test equipment that runs at-speed. Synopsys Inc., Mountain View, also lacks a BIST product in its portfolio, preferring to concentrate on scan technology, says David Hsu, senior product marketing manager. But the company is keeping its options open regarding introducing a BIST product in the future, he adds. Vendors of ATE equipment don't expect BIST will put them out of business any time soon. "I view BIST as a necessary but not sufficient approach," says Thomas Newsom, business development director for Hewlett-Packard Co.'s Automated Test group in Loveland, CO. "You can use a less complex tester than otherwise needed, but less complex than today? I don't know. When boundary scan was introduced, we heard about how we'd be able to use a 4-wire tester, but it never came to be. We're putting so much functionality on the chip that just to stay even is a challenge. |
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