Contents of the book "Design for Test. For IC's and Embedded Core Systems" by Alfred L. Crouch.

1. TEST AND DESIGN-FOR-TEST FUNDAMENTALS.

1.1. Introduction to Test and DFT Fundamentals.
1.2. The Reasons for Testing.
1.3. The Definition of Testing.
1.4. Test Measurement Criteria.
1.5. Fault Modeling.
1.6. Types of Testing.
1.7. Manufacturing Test.
1.8. Using Automatic Test Equipment
1.9. Test and Pin Timing.
1.10. Manufacturing Test Program Components.

2. AUTOMATIC TEST PATTERN GENERATION FUNDAMENTALS.

2.1. Introduction to Automatic Test Pattern Generation.
2.2. The Reasons for  ATPG.
2.3. The Automatic Test Pattern Generation Process.
2.4. Introducing the Combinational Stuck-At Fault.
2.5. Introducing the Delay Fault.
2.6. Introducing the Current-Based Fault.
2.7. Testability and Fault Analysis Methods.
2.8. Fault Masking.
2.9. Stuck Fault Equivalence.
2.10. Stuck-At ATPG
2.11. Transition Delay Fault ATPG
2.12. Path Delay Fault ATPG
2.13. Current-Based Fault ATPG
2.14. Combinational versus Sequential ATPG
2.15. Vector Simulation
2.16. ATPG Vectors.
2.17. ATPG-Based Design Rules.
2.18. Selecting an ATPG Tool.
2.19. ATPG Fundamentals Summary.
2.20. Recommended Reading.

3. SCAN ARCHITECTURES AND TECHNIQUES.

3.1. Introduction to Scan-Based Testing.
3.2. Functional Testing.
3.3. The Scan Effective Circuit
3.4. The Mux-D Style Scan Flip-Flops
3.5. Preferred Mux-D Scan Flip-Flops
3.6. The Scan Shift Register or Scan Chain
3.7. Scan Cell Operations
3.8. Scan Test Sequencing
3.9. Scan Test Timing
3.10. Safe Scan Shifting.
3.11. Safe Scan Sampling: Contention-Free Vectors
3.12. Partial Scan.
3.13. Multiple Scan Chains.
3.14. The Borrowed Scan Interface.
3.15. Clocking, On-Chip Clock Sources, and Scan.
3.16. Scan-Based Design Rules.
3.17. Stuck-At (DC) Scan Insertion.
3.18. Stuck-At Scan Diagnostics.
3.19. At-Speed Scan (AC) Test Goals.
3.20. At-Speed Scan Testing.
3.21. The At-Speed Scan Architecture.
3.22. The At-Speed Scan Interface.
3.23. Multiple Clock and Scan Domain Operation.
3.24. Scan Insertion and Clock Skew.
3.25. Scan Insertion for At-Speed Scan.
3.26. Critical Paths for At-Speed Scan.
3.27. Scan-Based Logic BIST.
3.28. Scan Test Fundamentals Summary. 
3.29. Recommended Reading.

4. MEMORY TEST ARCHITECTURES AND TECHNIQUES.

4.1. Introduction to Memory Testing.
4.2. Types of Memories.
4.3. Memory Organization.
4.4. Memory Design Concerns.
4.5. Memory Integration Concerns.
4.6. Embedded Memory Testing Methods.
4.7. The Basic Memory Testing Model.
4.8. The Stuck-At Bit-Cell Based Fault Models.
4.9. The Bridging Defect-Based Fault Models.
4.10. The Decode Fault Model.
4.11. The Data Retention Fault.
4.12. Diagnostic Bit Mapping.
4.13. Algorithmic Test Generation.
4.14. Memory Interaction with Scan Testing.
4.15. Scan Test Memory Modeling.
4.16. Scan Test Memory Black-Boxing.
4.17. Scan Test Memory Transparency
4.18. Scan Test Memory Model of the Fake Word.
4.19. Memory Test Requirements for MBIST
4.20. Memory Built-In Self-Test Requirements
4.21. An Example Memory BIST.
4.22. MBIST Chip Integration Issues.
4.23. MBIST Integration Concerns.
4.24. MBIST Power Concerns.
4.25. MBIST Design - Using LFSRs
4.26. Shift-based Memory BIST
4.27. ROM BIST
4.28. Memory Test Summary
4.29. Recommended Reading

5. EMBEDDED CORE TEST FUNDAMENTALS

5.1. Introduction to Embedded Core Testing.
5.2. What is a Core?
5.3. What is Core-Based Design?
5.4. Reuse Core Deliverables.
5.5. Core DFT Issues.
5.6. Development of ReUsable Core
5.7. DFT Interface Considerations - Test Signals
5.8. Core DFT Interface Concerns - Test Access
5.9. DFT Interface Concerns - Test Wrappers
5.10. The Registered Isolation Test Wrapper.
5.11. The Slice Isolation Test Wrapper.
5.12. The Isolation Test Wrapper - Slice Cell
5.13. The Isolation Test Wrapper - Core DFT Interface
5.14. Core Test Mode Default Values
5.15. DFT Interface Wrapper Concerns.
5.16. DFT Interface Concerns - Test Frequency.
5.17. Core DFT Development.
5.18. Core Test Economics.
5.19. Chip Design with a Core. 
5.20. Scan Testing the Isolated Core.
5.21. Scan Testing the Non-Core Logic
5.22. User Defined Logic Chip-Level DFT Concerns
5.23. Memory Testing with BIST.
5.24. Chip-Level DFT Integration Requirements.
5.25. Embedded Test Programs.
5.26. Selecting or Receiving a Core.
5.27. Embedded Core DFT Summary.
5.28. Recommended Reading.