In this project (project 3A), our group is to design a machine for function decompansition. This project has 6 parts for 6 student, and my task is to design the machine for variable partitioning.
At first, read first two data from ROM and saved them to "cellreg" and "varreg", these two registers, such that the machine can know how many minterms and how many variables (primary inputs) need to handle.
Then , pick up each minterm to count the 0's and 1's output numbers for specified variable. After counting the last minterm saved in ROM , a substractor will substract these two numbers and save it to register. This procesure will keep going until the machine count the last variable, and goes into the 3rd step.
In 3rd step, a sorter will sort all of the data saved in the registers, and note the variable order according to the difference between fanout "0" and fanout "1".

Basically, this machine is composed by 16 modules, and the black bold charactors used on each module in above blocks is the names of VHDL modules.

In order to reduce the operation complexsity, the data we used to partitioning is stored in ROM module. (So, at this time , no other ways to change the data saved in ROM but recomplie the whole project file.) The data saved in ROM is based on "cell", each cell has 8 bits and the first two cell has special meaning: 1st cell stores the minterm numbers of current project, 2nd cell stores the variable numbers of current project.
Then, the following data are minterm with the LSB is fanout, and other bits are primary inputs.(so, at this time, the most number of primary inputs of this machine is not great than 7, but it is very easy to enlarge primary inputs numbers. )

Because we use ROM to save input date, the interface with other student's project becomes very easy. The totally handshaking signals are "start", "clk" and "done" (all of them are std_logic) which can be used to controll this project by other VHDL module . And the rest signals are internal signal
when "start" is low, the "sys_clr" will be high.So the machine is in initial state. Otherwise, the machine is working.
"clk" is the system clock, all of the machine running are under this signal.
when "done"goes high, that means current project running is done, and main controller can let next stage to access data.

(1) When "start" is in low, the machine is in Inital state ,and all the modules cann't work.
(2) When "start" goes high, the machine starts to work. At first it copies the first two cells'data of ROM into "cellreg" and "varreg" seperately, these two data will controll how many times the machine will work.
(3) Then, the machine will get another data from ROM and count its 0's or 1's number for its fanout.
(4) Probe whether or not the data locked in "cellreg" is equal to the "rom_addr" if they are equal, that means counting for all of minter of current variarble is done,so substracts the "cnt1data" with "cnt0data" and saves data "sub_data" into "(q0...q7)" ,then goes to (5), otherwise, increase the romaddress and goes to (3).

NOTE: "(q0...q7)" is composed by "sub_data" and "sel_vec", the low 4bits of "(q0...q7)" is "sel_vec" low 4bits to show its's variable ID, and the high 4bits of "(q0...q7)" is the low 4bits of "sub_data" to show the substract result.

(5) Probe whether or not the data locked in "varreg" is equal to "sel_vec", if they are equal, that means the job of counting 0's and 1's number for each variable is done and goes to (6), otherwise, the machine needs to reset the "rom_addr" to count 0's and 1's number for a new variable from the first minterm saved in ROM.
(6) Start sorter to sort the data saved in "(q0 ... q7)", the principle of this sorter is based on Project <1>. After 3 clock pulse, the data will be sorted and the controller use "sorter_oe" this signal to send the result to "(O0...O7)"
. Also,at same time the controller will use "done" this signal to note all of the job is done, and the data can be accessible.

1). Input data
There are 6 variables and 6 minterms in this simulation.

x"06",
x"06",
x"ff",
x"a7",
x"81",
x"50",
x"FF",
x"1F",