Spread Spectrum Tranmsitter with arbitrary spreading sequences and programmable FIR filter.
Steven Harwood and Andrew Iverson
- Zipped file
ECE572_SS.zip with this project
- Power Point file
ece572_project.ppt that contains the entire description of the project
- PDF file
ece572_project.PDF that contains the entire description of the project
- Verilog file accum.v
that contains the description of the accumulator
- Verilog file add_dec.v
that contains the description of the RAM adder
- Verilog file clk_mod.v
that contains the description of the clock module
- Verilog file control.v
that contains the description of the Control Unit.
Control Unit talks to outside world (uP interface) and stores
data for the rest of the chip. Has interfaces to fifo, spreader,
and FIR filter.
- Verilog file dff.v
that contains the description of the D flip-flop
This is a D-Flip Flop with active low reset and active low preset
for Pseudo Random Bit Sequence Generator.
- Verilog file fifo.v
that contains the description of the FIFO
This is a 8-bit FIFO with push and pop clocks. It is 32 bytes deep.
- Verilog file
fifo_ram.v that contains the description of the 32 byte FIFO RAM block.
- Verilog file filt.v
that contains the description of the Baseband FIR filter block
Here the FIR RAM address is generated, based on whether
we are in program mode or not.
The two 6-operand accumulators are instantiated, as are
the two accumulator pipeline registers, and these partial
sums are added together in the final summation. The final summation
is large enough (by default) so that no overflow will occur.
- Verilog file fir12.v
that contains the description of the FIR filter
This module is the top level of the FIR filter for the spread spectrum
modulator project.
The filter is an upsampling (by four) FIR lowpass filter. So, for every
one data input sample, there are four output samples. Further, to make
use of the higher clock frequency capablities of the Xilinx FPGA's, both
the I and Q channel FIR filters are implemented in a single, multiplexed,
filter (the filters are identical). This pushes the filter to operate at
a higher data rate, but makes up for it in cost savings.
Due to the multiplexing and upsampling operations, several small state
machines are required for desired operation.
- Verilog file fpga.v
that contains the description of the Top level FPGA module
Spread Spectrum Tranmsitter with arbitrary spreading sequences and programmable FIR filter.
Authors: Steve Harwood and Andrew Iverson, 12-10-99.
- Verilog file p2s.v
that contains the description of the
Parallel to Serial shift register module. 8bits in, 1 bit out MSB first.
Negedge of s_clk && load causes new data to be loaded into the shift register.
Serial data is shifted out on the negedge of the s_clk, so the data is
valid on the posedge.
- Verilog file prbs.v
that contains the description of the PRBS
Completely reconfigurable Pseudo Random Bit Sequence Generator
tap_config = 0 means that there will be no feedback for that
particular tap. Ensure that your last_tap is the last "1" in
the tap_config input. ex: 000...00010100 would mean that
your feedback equation was 1 + x^3 + x^5, and if last_tap
is set to 000101, then you're fine because you're last tap is in position #5.
- Verilog file ram_fir.v
that contains the description of the RAM FIR
16 deep x 12 wide synchronous RAM.
In this application, the bottom 8 addresses are loaded with
appropriate non-zero FIR filter tap values. The top 8 addresses are loaded
with zero for occasions where the data into the FIR is zero.
- Verilog file shift_reg.v
that contains the description of the 12-bit shift register
- Verilog file spreader.v
that contains the description of the Spreader
Spreading block that takes a serial bitstream as input and
outputs an I and Q "spread" signal. Uses the prbs module.
- Verilog file udcount.v
that contains the description of the UD count
6-bit up down counter with async reset.