TEST, DESIGN FOR TEST, DESIGN FOR SELF-REPAIR

SELF-TEST OF EASILY TESTABLE CIRCUITS

• Ugur Kalay, Marek Perkowski, Doug Hall, ``A Minimal Universal Test Set for Self-Test of EXOR-Sum-Of-Products Circuits,'' IEEE Tr. on Computers, March 2000, Vol. 49, pp. 267 - 276.
  
  
• Ugur Kalay, Douglas V. Hall, and Marek Perkowski ``Easily Testable Multiple-Valued Galois Field Sum-of-Products Circuits''. Journal on Multiple Valued Logic, 2000, Vol. 5, pp. 507-528.
  
  
• Ugur Kalay, Douglas Hall, and Marek Perkowski, ``Highly Testable Boolean Rings,'' Proc. ISMVL'99, Freiburg, Germany, 17-21 May, 1999.
  
  
• Ugur Kalay, Marek Perkowski, Douglas Hall, Bernd Steinbach, and Shah Amran Shahjahan, ``Rectangle Covering Factorization of ESOPs into Scan-Based Levelized Circuits with Universal Test Set,'' Proceedings of RM'99.
  
  
• Ugur Kalay, Douglas Hall, and Marek Perkowski, ``Easily Testable Multiple-Valued Galois Field Sum-of-Products Circuits,'' Proc. of ULSI Workshop, Japan, May 1998.
  
  
• A. Sarabi, M. A. Perkowski, "Design for Testability Properties of AND/XOR Networks," Proc. of IFIP W.G. 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design," Hamburg, Germany, September 16-17, pp. 147 - 153, 1993.
  
  
  
• Andisheh Sarabi, and Marek A. Perkowski, "Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks," Proc. of the IEEE/ACM Design Automation Conference, pp. 30 - 35, Anaheim, CA, June 8-12, 1992.
  
  

SELF-REPAIR OF REGULARLY STRUCTURED CIRCUITS

• Dipal
  
  
  
  
• Chong-Ho Lee, Marek Perkowski, Douglas Hall, and David Jun, ``Self-Repairable EPLDs II: Advanced Self-Repairing Methodology''. Proc. of the 2001 Congress on Evolutionary Computation (CEC2001), pp. 616 - 623, May 27-30, 2001, COEX Center, Seoul, Korea.
  
  
• Chong-Ho Lee, Douglas Hall, Marek Perkowski, David Jun, ``PLD with self-repair,'' Journal on System Architecture. accepted. 2001.
  
  
• Chong-Ho Lee, Marek Perkowski, Douglas Hall and David Jun, ``Self-repairable EPLDs: Design, Self-Repair, and Evaluation Methodology,'' Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, Evolution in Silicon, 13-15 July, 2000, Palo Alto, California, pp. 183 - 193.
  
  
• Perkowski Minnesota,
  
  

TEST GENERATION FOR COMBINATIONAL CIRCUITS

• Alan Mishchenko, Bernd Steinbach, and Marek Perkowski, ``An Algorithm for Bi-Decomposition of Logic Functions,'' Proceedings of Design Automation Conference, DAC 2001, June 18-22, Las Vegas, pp. 103 - 108.
  
  FOR NEXT PAPER: SHOW HOW TO GENERATE TESTS AS BYPRODUCT OF SYNTHESIS.
  
  
• Lech Jozwiak, Aleksander Slusarczyk, Marek Perkowski, ``AND/EXOR Trees for Testability,'' VLSI Design. Accepted. 2001.
  
  
• Lech Jozwiak, Aleksander Slusarczyk, and Marek Perkowski, ``AND/EXOR Trees for Testability,'' Proc. International Workshop on Applications of the Reed-Müller Expansion in Circuit Design (Reed-Müller 99), University of Victoria, Victoria B.C., Canada, August 20-21, 1999.

TEST GENERATION AND DESIGN FOR TEST OF SEQUENTIAL CIRUITS

• Nagesh Venkataramaiah, Karen Dill, Doug Hall, Marek Perkowski, Alan Mishchenko, Ugur Kalay, ``Highly Testable Finite State Machines Based on Exor Logic,'' Proc. 7th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM '99), Victoria, B.C., Canada, August 23-25, 1999, pp. 440-443. postscript PACRIM'99
  
  
• Marek Perkowski, "An Application of Heuristic Search Strategy in the Multiple, Adaptive Identification Experiment with Finite State Machines," Proc. of the First National Symposium on Heuristic Methods, pp. 135 - 152, (in Polish), Polish Cybernetical Society, PTC, Warsaw, 28 Sept. 1974.

SCAN DESIGN

• H. Wu, M. A. Perkowski, "Novel CMOS Scan Design for VLSI Testability," IEE Proceedings, , Pt. E.
  
  
  
• H. Wu, N. Zhuang, M. A. Perkowski, "Novel CMOS Scan Design for VLSI Testability," Proc. of the 23nd IEEE International Symposium on Multiple Valued Logic, ISMVL '93, pp. 82 - 86, Sacramento, CA, May 24-27, 1993.