Multi-Level Cell (MLC) technology enables storage of multiple bits per memory cell by charging the polysilicon floating gate of a transistor to different levels. This technology takes advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range. MLC effectively reduces cell area as well as the die size for a given density. This ultimately leads to a significantly reduced unit cost-per-megabyte --one of the greatest benefits of this technology. Today’s MLC memory products are capable of storing two bits per memory cell (Figure 1, b). The MLC technology path illustrates that NOR-based MLC technology is easily scaleable to three bits-per-cell (Figure 1, c), which enables another significant increase in density per area.
In MLC technology, the voltage across each cell has been divided into greater than two levels. Figure 1 illustrates Vt level placement for two and three bit-per-cell technology.
MLC Cell Operations
MLC Program Operation
During programming, each cell’s direct ground, bitline, and wordline connection
enables precise charge placement. A cell’s control gate links to the internally
generated supply voltage through a direct wordline connection and row decoding. The
drain is pulsed at a constant voltage through a direct bitline connection and column
decoding. The source is directly connected to ground (Figure 2, a).
Electron storage on the floating gate creates a potential that must be overcome by
the control gate. This potential results in a higher turn-on threshold
voltage (V
MLC devices must be able to
manage electrical charge precisely. More specifically, these devices must be able
to place charge with precision, sense charge with precision,
and store charge over time. These requirements are met by the NOR
architecture’s direct connection to the gate, source, and drain of each
memory cell. Each cell is made up of a single transistor which is directly
connected to the appropriate control voltages in order to accomplish pinpoint accuracy
in charge manipulation.
During programming,
a precise charge must be placed onto the floating gate. The analog voltage that
exists across each flash cell is divided into
multiple Vt levels which are controlled
by the amount of electrons on the floating gate. Channel Hot-Electron (CHE) injection
controls this charge placement.
In MLC technology, the voltage across each cell has been divided into multiple levels. Figure 4 illustrates cell distribution over individual voltage levels, along with the placement reference points (P1, P2, and P3) for two bit-per-cell technology. During programming, a specific voltage range is used to represent one of the specific levels. Programming data at a given memory address transitions selected cells from the "11" (erased) level to the "10," "01," or "00" (programmed) levels. Storing two bits-per-cell requires four levels defined by read reference cells; R1, R2, and R3. These voltage levels are defined by the threshold voltage of the read reference cells as follows: Vt <; Vt(R1) is level 0, Vt(R1) <; Vt <; Vt(R2) is level 1, Vt(R2) <; Vt <; Vt(R3) is level 2, and Vt >; Vt(R3) is level 3. Specific, unique voltage values define each level.
MLC Read Operation
The data read operation senses which of the four levels the memory cell
falls within based on the threshold voltages of the three read reference
cells. The reference cells are biased in such a way that each conducts
a current proportional to the Vt of its specific level.
During the read operation; VREAD is placed on the
control gate, the source is grounded, and a drain bias is applied. In this mode, a
cell conducts a current (ICell) which is
proportional to the cell’s Vt.
When the cells are biased in this way, the current conducted through each
cell has an inverse relationship to its Vt.
Therefore, if current through the flash array cell is greater than the
appropriate reference current (ICell
>; I
R#Ref ) then
the memory cell Vt is less then the reference
cell Vt (VtCell<; VtRef). The data is read by comparing the current through the memory cell to the current through three read reference cells.
The bitline current for the memory cell is compared to the current produced
by three read reference circuits. The current is sensed by connecting the
drain to an active load, which is connected to a differential sense amplifier.
For a read operation, there is a sense amplifier for each of the three read
reference cells. Each sense amplifier has a flash array input, from the bitline,
and a reference cell input.
If I Cell >; IR# the sense amplifier outputs a logic "1."
The outputs of the three sense amplifiers are connected to a logic circuit
which interprets the two data bits in parallel. If the memory cell is in
level 0 then I Cell
>; I R1Ref. Therefore, all of the sense amplifiers output a logic "1" and the logic circuit outputs the data "11." In level 1, I R2Ref <; I Cell <; I R1Ref, so sense amplifier 1 outputs a logic "0" and sense amplifiers 2 and 3 output a logic "1" The logic circuit interprets these outputs to be data "10." In level 2, I R3Ref
<; I Cell <; I R2Ref, so sense amplifiers 1 and 2 output a logic "0" and sense amplifier 3 outputs a logic "1." The logic circuit interprets these outputs to be data "01." Finally in level 3, I
Cell <; I
R2Ref, so all the sense amplifiers output a logic "0" and the logic circuit outputs the data "00."
The sensing operation described here for the data read operation is
also used in the program operation. During the program operation, sensing
is done to ensure that the memory cell has reached the desired level.
MLC Technology Advantages
Lower Cost
Other Flash Memory Technology Advantages
During data read, charge sensing
is of maximum importance. Through direct connections to each memory cell, the
data read operation determines the level of each memory cell quickly,
accurately, and reliably. Read speeds are comparable to single bit-per-cell technology.
There are many advantages
associated with the use of flash memory. The
solid-state nature of flash provides ruggedness far superior to mechanical
rotating media. Not only is MLC memory valuable as a digital media, but advantages
such as direct access to each cell, specific to NOR-based flash architectures, permit
reliable charge placement, sensing, and storage.
Cost relates directly to die
size. The smaller the die size, the lower the cost. Dramatic cost breaks are associated
with the MLC technology approach because, at two bits-per-cell, the density of the
device is doubled without increasing the die size. This becomes even more apparent at
three bits-per-cell, where the density of bits-per-cell will triple without significantly
increasing die size!
