Maximum Clique and Bound Set Encoding

Wei Wang

weiwang@ee.pdx.edu

EE510VH: VHDL Design

Portland State University, Portland OR



Algorithm
Circuit Architecture and Design
Simulation Results
VHDL Files

Given the Compatability Graph, we use the maximum clique algorithm to figure out the column multiplicity and then encode the bound set. Maximum clique problem is basically a NP complete problem, there are many heuristics proposed. The major concern to choose which algorithm would be the trade off between efficiency and time. In our application, time is the most important, at the same time, because that we are going to map our design to DECPeRLe Board, we can also consider to implement it in a regular or pipelining structure to maximumly utilize the resource. The Maximum clique problem can be also formulated as graph coloring problem, the graph for graph coloring problem will be complementary to the graph for the Maximum clique problem.



I. Maximum Clique Problem

1. Algorithm description

Given the column compatability graph below:




We will use color to represent clique, i.e., the problem becomes find the maximum cliques in the graph and color vertices such that vertices in one clique have the same color. 1. Initialize each node with the same color:




2. For each node, compare with any other node in the graph,
If these two nodes are compatible
keep current color
else if these two nodes are of different color
keep current color
else
change the color of the other node to next available color
endif
endif
Following the above steps, we have:


In the first 2 comparison, the color of node 1, 2 and 7 is kept (A) because they are compatible, the color of the other nodes is changed to color B.


In comparison for node 3, the color of node 1, 2,and 7 is kept because they are imcompatible with node 3 and their color is different from node 3. The color of the incompatilbe node 4, 5 and 6 is changed to color C.


Following the same rule, the next comparison for node 4 will keep color C for the two compatible node 4 and 6, and assign color D to node 5.

II. Circuit Architecture and Design

1. Maximum Clique Algorithm Process Element(PE)

Based on the above algorithm, the main data_path computation will be the comparison and color assignment for each node. We can look computation component as a Process Element for vertices. If we assign each vertice a PE, it will be a very regular structure.


From the algorithm, we have the following logic relation:


From this table, suppose the compatability is A, the output from comparator is B, Then A .OR. B can be used as the multiplexor control signal to select whether we keep or change the color. This logic is implemented with a comparitor, multiplexor and a OR gate.



2. Data path

The data path block diagram is shown below. Suppose we have 16 columns at most and each column is encoded with 4 bits. register R0 is to store the # of columns(vertices), R1 is to store the compatibility graph, each row at a time. R2 is the output register to store the encoded column code during output. Register C0-C15 is the encoded column value, PE0-PE15 is the process element for each column. The column number counter and 4-bit comparator are used to count the column we computed. The output of the counter is also the 16x1 MUX control signal, which select the common column to be compared with other columns. After we finish comparing each column, the column number counter is set to 0 and start to count again, the output tri-buffer will open now thus output the encoded column code to data bus.




3. Circuit block diagram

The circuit is composed of 4 main components:





The block diagram for the circuit is shown below.






4. Control Unit

Control Unit control the timing of the whole system. The timing is based on the computation flow chart. The flow chart is shown below:




The state transition diagram is shown below:




The control unit by vhdl is writen in a behaviour model.

III. Simulation Results

1. Data path Unit:
Given the graph shown at the beginning, the simulation result for the comparison and computation process is shown below. In the simulation, at first every column code are initialized as 0, by the first comparion for column 0, because it is compatable with column 1 and 6, their column code keep the same value, other column code(for column 2,3,4,5,7) change to the next color 1. By repeating comparison for each column, we can see every column is encoded and compatable columns have the same code.




The next simulation result shows the column codes sequence are written to data_bus one by one. We can see that the encoded column are:

Column 0: 0
Column 1: 0
Column 2: 1
Column 3: 2
Column 4: 3
Column 5: 2
Column 6: 0
Column 7: 1




2. Control Unit:





Appendix A: VHDL Program Source Code


Maximum clique and column encoder system(very top level)
Control Unit
Maximum clique process element
Data pathUnit
a 16x8 RAM
4-bit address register
16-bit register
16x1 4-bit multiplexer array
all other small cells are availaber here!