ECE 590. DIGITAL SYSTEM DESIGN USING HARDARE DESCRIPTION LANGUAGES.



THIS IS A MANDATORY READING MATERIAL FOR THE "VHDL CLASS". This class teaches much more than only VHDL language. The main goal is to teach about specifying practical digital systems, simulating and synthesizing to FPGAs.


IF SOMETHING IS NOT CLEAR, PLEASE SEND ME AN EMAIL OR TALK TO ME AND I WILL UPDATE THE PDF FILES AND ADD MORE EXAMPLES.

You should be able to solve all problems given at the end of a file.



Here are the lectures from other classes that may be useful as a background.
  1. ECE 271. Digital System Design. Second class in digital design at PSU. State machines, digital systems, VHDL, intro to test.
  2. ECE 572. Advanced Logic Synthesis. Introductory graduate class. Logic synthesis theory, decomposition, multi-valued logic, Reed-Muller and Galois circuits.
  3. ECE 510DT. Test and Design for Test.
  4. ECE 478. Intelligent Robotics 1.
Portland State University
College of Engineering and Computer Science
ECE 590. VHDL Design.
Course Schedule, Spring 2006
Updated March 12, 2006


Wk 
Date 
Subject 
Required
Reading 
Additional
Reading 
Homeworks and Projects
1 
FUNDAMENTALS OF VHDL AND PROJECTS.
Monday
April 3
  1. Class organization. Projects. Grading. Exams.
  2. REVIEW: Flip-Flops. Shifts. Generalized Registers. Register Transfer and Kmaps.
  3. Introduction to VHDL. Design styles. Behavioral, functional and structural descriptions.
  4. Objects, Types and Operations.
  1. SLIDES: Lecture 1, about class and review. incomplete.
  2. SLIDES: Lecture 2. Diagrams and VHDL Intro.
  1. Review chapters 1 - 5 in textbook.
  1. INTRODUCTORY HOMEWORK.
    This is just to create your WWW Page for this class. It does not qualify as one of two "official" homeworks (mini-projects) for this class.

    Create your own WWW Page for this class.

    Write about your interests in VHDL, digital design, design automation, ASIC design, computer architecture and related topics.

    Add links to the pages of your interest from the WWW.
  2. Short discussion of class projects for this quarter, and creation of project groups.

  3. PROJECT. Read project descriptions and related links. Start thinking what will be your project for this class. Talk to me about project.
  4. GOOD WWW PAGE RESOURCES TO CREATE YOUR OWN PAGES.
  5. NTU INTRANET HOME PAGE --- Source of courses in Logic Synthesis.
Wednesday,
April 5
  1. Continuation on basic VHDL. Examples of descriptions of simple machines and logic and sequential blocks.
  2. Register Transfer description.
  1. My class notes.
  2. Previous student projects.
  3. PDF Fil: Example of good homework 1 design and documentation.
  4. PDF Fil: Modeling Tool Use
  1. Review Kohavi's textbook on basic material and state machines.
  2. You can use also Mano/Kime, Roth or Wakerly texbooks.
  1. OFFICIAL HOMEWORK NUMBER ONE.

    Select the homework topics:
    1. from my WWW page,
    2. from any book on VHDL,
    3. as a part of your final project,
    4. presented or mentioned in VHDL class,
    5. or any problem in VHDL of your interest.


    It should be a large combinational circuit with hierarchy, a state machine, a data path or a controller composed of a controlling state machine and data path controlled by it. This homework should be simple but not trivial and should be done by a single person, not a group. However, working on homeworks and projects in groups and learning EDA tools together is highly recommended. Just the final work of writing code and testing it is an individual assignment. In projects you will work together on everything.
Wk 
Date 
Subject 
Required
Reading 
Additional
Reading 
Homeworks and Projects
2 
SEQUENTIAL STATEMENTS AND FINITE STATE MACHINES.
Monday,
April 10
  1. Sequential statements.
  2. Structural modeling.
  3. Data Flow modeling.
  4. Finite State Machines.
  1. SLIDES: Lecture 3 of Kerntopf about reversible logic fundamentals.
  2. SLIDES: Timing and Simulation
  3. SLIDES: Mentor Graphics Tools.
  1. Complete reading in Kohavi about FSMs, and if necessary, previous chapter(s).
  2. You can use also Mano/Kime, Roth or Wakerly texbooks. I found Roth and Mano/Kime particularly useful for beginners.
HOMEWORK 2. This homework must include Finite State machine as its part and must have synthesis with discussion of variants. Otherwise you are free to select any topic of your interest.
Wednesday,
April 12
  1. Data flow modeling.
  2. Complete descriptions of Finite State Machines.
  1. SLIDES: Robot Design. Example of a complete state machine
  2. SLIDES: Modelsim Tools Advise
  3. SLIDES: Cube Calculus
  4. SLIDES: Learnining Hardware and Evolvable Hardware
  5. SLIDES: Cube Calculus Machine Architecture Fundamentals
  1. SLIDES: Data Flow Modeling.
  2. Read Kohavi about structural design of FSMs. You can use also Mano/Kime, Roth or Wakerly texbooks.
Continue working on the project.
3 
DESIGN OF COMPLETE REGISTER TRANSFER LEVEL CONTROLLERS IN VHDL.
Monday,
April 17
  1. Complete controller design.
  1. Combinational Circuits in VHDL
  2. Assignment Statements
    For material review, you can use also Mano/Kime, Roth or Wakerly texbooks.
    none.
Wednesday,
April 19. 		Student presentations about projects.
  1. Read chapter about combinational descriptions in VHDL from your textbook.
    none.
    none.
4 
COMBINATIONAL AND SEQUENTIAL BLOCKS. STRUCTURAL MODELING.
  1. Conditionals
Monday,
April 24
  1. Structural modeling.
  2. Review on logic blocks.
  1. Review on CAE tools and basic technologies in which FSMs are realized.
  2. SLIDES: Structural Modeling II.
  3. SLIDES: Modern Tools for VLSI.
  4. SLIDES: Design Methodologies in VLSI.
Wednesday,
April 26
  1. HOMEWORK ONE IS DUE TODAY
  2. REMINDER: HOMEWORK 2. This homework must include Finite State machine as its part and must have synthesis with discussion of variants. Otherwise you are free to select any topic of your interest. Use Leonardo or similar toold. Map to an FPGA.
  3. Combinational circuits in VHDL.
  4. Assignment statements.
  5. Technology review.
  1. Object types and operations
  2. CPLDs and FPGAs for our projects
  3. DSP Circuits
  • Review on logic and sequential blocks. Use of logic blocks in sequential machines.
  • Shifters, counters.
    1. SLIDES: Multiplexers, Decoders, ROMs. Use in design.
    2. SLIDES: PAL, PLA, EPLD, FPGA. Complex PLD (CPLD).
    3. SLIDES: Arithmetic Circuits. Full adder. Adder/Subtractor. Ripple Carry Chain. Carry Look-Ahead adder. Carry Select Adder. Generalization of these Principles.
    4. SLIDES: Arithmetic Circuits. Serial Adder. ALU, Parity. Comparators. Multiplier.
    5. SLIDES: Combinational circuits in VHDL.
    6. SLIDES: Assignment statements.
    7. SLIDES: Technology.
    		• First presentations of student projects.
    5 
    DESIGNING CONTROLLERS.
    Monday, May 1
    1. Conditionals.
    2. Basic Timing Model and simulation.
    3. Modeling Tools Use. How to use our tools. Very useful guidelines.
    1. SLIDES: Conditionals.
    2. SLIDES: Basic Timing Model and simulation.
    3. SLIDES: Modeling Tools Use.
    1. Book about Cellular automata.
    Wednesday,
    May 3
    1. Data Types.
    2. Modeling Constructs.
    1. SLIDES: Data Types.
    2. SLIDES: Modeling Constructs.
      Nothing.
    		No homework. Continue work on project.
    6 
    DESIGN OF DATA PATH LOGIC.
    Monday,
    May 8
    1. Procedures and functions.
    2. Test Benches.
    3. Overview of synthesis and synthesis tools.
    1. SLIDES: Procedures and Functions.
    2. SLIDES: Test Benches.
    3. SLIDES: Synthesis tools.
    		None. None.
    Wednesday,
    May 10     		Continuation on special purpose machines. None. None. None.
    7 
    LOGIC SYNTHESIS.
    Monday,
    May 15
    1. I AM ATTENDING ULSI AND ISMVL CONFERENCES.
    2. LECTURE BY ............
      SLIDES WILL BE PROVIDED IN FUTURE.
      .
      none.
    Wednesday,
    May 17
    1. I AM ATTENDING TWO CONDERENCES: INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC AND ULTRA-LARGE SCALE INTEGRATION WORKSHOP - BEYOND SILICON.

    2. TODAY CLASS WILL BE PROJECT AND HOMEWORKS PRESENTATIONS. THE STUDENT PRESENTATIONS WILL BE VIDEOTAPED AND STREAMED AND I WILL VIEW THEM WHEN I WILL BE BACK.
    3. PLEASE SUBMIT YOUR SLIDES IN PPT TO ME.
    1. none.
    1. none.
    8  
    COMPUTER ARCHITECTURES AND THEIR VHDL DESCRIPTIONS.
    Monday, May 22
    1. I AM BACK. HOMEWORK TWO IS DUE TODAY
    2. Introduction to EDA tools. Or, what is inside your VHDL-based tools.
    3. Systematic Designing of a microprocessor after Mano and Kime
    4. Basic Pipelining Techniques
    5. Basic Clocking Schemes Design
    6. Introduction to Parallel Computing and Processors
    7. Parallel Machine Classification
    8. Cellular Automata.
    1. SLIDES: Introduction to EDA tools.
    2. SLIDES: Microprocessor design. Mano and Kime
    3. SLIDES: Pipelining
    4. SLIDES: Clocking
    5. SLIDES: Parallel Computing
    6. SLIDES: Machine Classification
    7. SLIDES: Cellular Automata.
    1. none
      none
    Wednesday, May 24 Continuation on VHDL and parallel architectures.
      .
    9 
    DESIGNING NON-STANDARD FPGA COMPUTER ARCHITECTURES.
    Monday, May 29
    1. NO CLASS
    2. Systolic Processors. READ INDIVIDUALLY.
    3. Advanced and Reconfigurable Systolic Processors.
    4. DNA matching systolic architectures.
    5. Reconfigurable Pipelines.
    6. Very Long Instruction Word (VLIW) Architectures.
    7. Example of good student project. Software, hardware, VHDL. Use of parallel concepts from the class in project. Jacob Boles.
    8. Design of a Intel microcontroller in Xilinx.
    9. Design of a complete ASIC CPU.
    1. SLIDES: Systolic Processors.
    2. SLIDES: Advanced and Reconfigurable Systolic Processors.
    3. SLIDES: DNA matching systolic architectures
    4. SLIDES: Reconfigurable Pipelines
    5. SLIDES: VLIW Architectures
    6. SLIDES: Satisfiability machine of Boles.
    7. SLIDES: Design of a Intel microcontroller in Xilinx.
    8. SLIDES: Design of a complete ASIC CPU.
      none.
    Wednesday,
    May 31
    1. Continuation on complex architectures.
    1. None.
    1. none.
    1. none.
    10 
    LARGE PROCESSORS.
    VHDL TOOLS AND THEIR USE.
    Monday, June 5
    1. Packages and aliases.
    2. Processor design.
    3. System Level Modeling.
    1. SLIDES: Packages and aliases.
    2. SLIDES: DP32 Processor.
    3. SLIDES: DP Processor Components.
    4. SLIDES: System Level Modeling.
    1. none.
      none.
    Wednesday,
    June 7.
    1. PROJECTS.
    1. SLIDES PDF: Verilog Lecture in PDF
    2. SLIDES POWERPOING: Verilog Lecture in PPT
    1. SLIDES: ESA Coding Standards."
    2. SLIDES: Discrete Events Simulation.
      .
    11 
    PROJECT PRESENTATIONS
    Monday, June 12
    1. WEEKS OF FINALS. STUDENTS PROJECTS PRESENTATIONS.
    2. The presentations will be videotaped for me to view when I will be back.
    1. links to student www pages with projects.
    1. links to student www pages with projects.
    		This is the last week for presentations of projects.
    How to write the project report.
    no new reading. Please work on project report and slides.
    Wednesday,
    June 14
    1. THIS IS WEEK OF FINAL.
    2. Student Project presentations.
    		Work on project presentation and report. Work on project presentation and report. Project demonstrations. Complete past mini-projects and projects. Projects are due Sunday, June 18. I WILL GRADE THEM WHEN I WILL BE BACK, ON SUNDAY. YOU CAN EXPECT YOUR GRADE DELAYED BY TWO OR THREE DAYS.






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    You can reach me at
    mperkows@ee.pdx.edu